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參數(shù)資料
| 型號(hào)： | CY7C128A |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2K x 8 Static RAM(2K x 8 靜態(tài) RAM) |
| 中文描述： | 2K × 8靜態(tài)RAM（2K × 8靜態(tài)RAM）的 |
| 文件頁(yè)數(shù)： | 3/9頁(yè) |
| 文件大?。?/td> | 184K |
| 代理商： | CY7C128A |
CY7C128A
3
AC Test Loads and Waveforms
3.0V
5V
OUTPUT
R1 481
R2
255
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤
5 ns
≤
5 ns
5V
OUTPUT
C128A
–
4
R1 481
R2
255
5 pF
INCLUDING
JIG AND
SCOPE
C128A
–
5
(a)
(b)
OUTPUT
1.73V
Equivalent to:
TH
é
VENIN EQUIVALENT
167
ALL INPUT PULSES
Switching Characteristics
Over the Operating Range
[2, 6]
7C128A-15
Min.
7C128A-20
Min.
7C128A-25
Min.
7C128A-35
Min.
7C128A-45
Min.
Parameter
Description
Max.
Max.
Max.
Max.
Max.
Unit
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
[9]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Notes:
6.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
7.
t
, t
, and t
are specified with C
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady state voltage.
8.
At any given temperature and voltage condition, t
is less than t
for any given device.
9.
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Read Cycle Time
15
20
25
35
45
ns
Address to Data Valid
15
20
25
35
45
ns
Data Hold from Address Change
5
5
5
5
5
ns
CE LOW to Data Valid
15
20
25
35
45
ns
OE LOW to Data Valid
10
10
12
15
20
ns
OE LOW to Low Z
OE HIGH to High Z
[7]
CE LOW to Low Z
[8]
CE HIGH to High Z
[7, 8]
3
3
3
3
3
ns
8
8
10
12
15
ns
5
5
5
5
5
ns
8
8
10
15
15
ns
CE LOW to Power-Up
0
0
0
0
0
ns
CE HIGH to Power-Down
15
20
20
20
25
ns
Write Cycle Time
15
20
20
25
40
ns
CE LOW to Write End
12
15
20
25
30
ns
Address Set-Up to Write End
12
15
20
25
30
ns
Address Hold from Write End
0
0
0
0
0
ns
Address Set-Up to Write Start
0
0
0
0
0
ns
WE Pulse Width
12
15
15
20
20
ns
Data Set-Up to Write End
10
10
10
15
15
ns
Data Hold from Write End
WE LOW to High Z
[7]
0
0
0
0
0
ns
7
7
7
10
15
ns
WE HIGH to Low Z
5
5
5
5
5
ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C128A-15PC | 功能描述:IC SRAM 16KBIT 15NS 24DIP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| CY7C128A-15VC | 功能描述:IC SRAM 16KBIT 15NS 24SOJ RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| cy7c128a-15vct | 制造商:Cypress Semiconductor 功能描述: |
| CY7C128A-20SCT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| CY7C128A-20VC | 功能描述:IC SRAM 16KBIT 20NS 24SOJ RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
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