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參數(shù)資料
| 型號： | CY7C1256V18-300BZXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| 中文描述： | 4M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 1042K |
| 代理商： | CY7C1256V18-300BZXI |
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CY7C1241V18
CY7C1256V18
CY7C1243V18
CY7C1245V18
Document Number: 001-06365 Rev. *C
Page 10 of 28
Application Example
Figure 1
shows the use of 4 QDR-II+ SRAMs in an application.
Figure 1. Application Example
Truth Table
The truth table for the CY7C1241V18, CY7C1256V18, CY7C1243V18, and CY7C1245V18 follows.
[2, 3, 4, 5, 6, 7]
Operation
K
RPS WPS
DQ
DQ
DQ
DQ
Write Cycle:
Load address on the
rising edge of K; input
write data on two
consecutive K and K
rising edges.
L-H
H
[8]
L
[9]
D(A) at K(t + 1)
↑
D(A + 1) at K(t +1)
↑
D(A + 2) at K(t + 2)
↑
D(A + 3) at K(t + 2)
↑
Read Cycle:
(2.0 cycle Latency)
Load address on the
rising edge of K; wait
two cycle; read data
on two consecutive K
and K rising edges.
L-H
L
[9]
X
Q(A) at K(t + 2)
↑
Q(A + 1) at K(t + 2)
↑
Q(A + 2) at K(t + 3)
↑
Q(A + 3) at K(t + 3)
↑
NOP: No Operation
L-H
H
H
D = X
Q = High-Z
D = X
Q = High-Z
D = X
Q = High-Z
D = X
Q = High-Z
Standby: Clock
Stopped
Stopped X
X
Previous State
Previous State
Previous State
Previous State
BUS MASTER
(CPU or ASIC)
DATA IN
DATA OUT
Address
Source K
Source K
Vt
Vt
Vt
R
R
CLKIN/CLKIN
D
A
K
SRAM #4
RQ = 250
ohms
ZQ
CQ/CQ
Q
K
RPS WPS BWS
D
A
K
SRAM #1
RQ = 250
ohms
ZQ
CQ/CQ
Q
K
RPS WPS BWS
RPS
WPS
BWS
R = 50ohms, Vt = VDDQ
R
Notes
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
↑
represents rising edge.
3. Device will power-up deselected and the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.
5. “t” represents the cycle at which a Read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the
“t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.
7. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will
ignore the second Read or Write request.
[+] Feedback
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