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| 型號(hào)： | CY7C1246V18-300BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| 中文描述： | 4M X 8 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁(yè)數(shù)： | 9/27頁(yè) |
| 文件大?。?/td> | 1037K |
| 代理商： | CY7C1246V18-300BZXC |
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CY7C1246V18
CY7C1257V18
CY7C1248V18
CY7C1250V18
Document Number: 001-06348 Rev. *C
Page 9 of 27
device along with data output. This signal is also edge aligned
with the echo clock and follows the timing of any data pin. This
signal is asserted half a cycle before valid data arrives.
Delay Lock Loop (DLL)
These chips use a DLL that is designed to function between
120 MHz and the specified maximum clock frequency. The
DLL may be disabled by applying ground to the DOFF pin.
When the DLL is turned off, the device behaves in DDR-I mode
(with 1.0 cycle latency and a longer access time). For more
information, refer to the application note,
DLL Considerations
in QDRII/DDRII/QDRII+/DDRII+
. The DLL can also be reset by
slowing or stopping the input clocks K and K for a minimum of
30 ns. However, it is not necessary for the DLL to be reset to
lock to the desired frequency. During power up, when the
DOFF is tied HIGH, the DLL gets locked after 2048 cycles of
stable clock.
Application Example
Figure 1
shows the use of two DDR-II+ in an application.
Figure 1. Application Example
Truth Table
The truth table for the CY7C1246V18, CY7C1257V18, CY7C1248V18, and CY7C1250V18 follows.
[2, 3, 4, 5, 6, 7]
Operation
K
LD
R/W
DQ
DQ
Write Cycle:
Load address; wait one cycle; input write data on consecutive
K and K rising edges.
L-H
L
L
D(A) at K(t + 1)
↑
D(A + 1) at K(t + 1)
↑
Read Cycle: (2.0 cycle Latency)
Load address; wait two cycle; read data on consecutive K and
K rising edges.
L-H
L
H
Q(A) at K(t + 2)
↑
Q(A + 1) at K(t + 2)
↑
NOP: No Operation
L-H
H
X
High-Z
High-Z
Standby: Clock Stopped
Stopped
X
X
Previous State
Previous State
BUS
MASTER
(CPU or ASIC)
DQ
Addresses
Cycle Start
R/W
Source CLK
Source CLK
Echo Clock1/Echo Clock1
Echo Clock2/Echo Clock2
R
= 250ohms
LD
R/W
DQ
A
SRAM#1
K
K
ZQ
CQ/CQ
R
= 250ohms
LD
R/W
DQ
A
SRAM#2
K
K
ZQ
CQ/CQ
Notes
2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW,
↑
represents rising edge.
3. Device powers up deselected with the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.
7. Cypress recommends that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
[+] Feedback
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