參數資料
型號: CY7C1168V18-300BZXI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
中文描述: 1M X 18 DDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁數: 15/27頁
文件大?。?/td> 963K
代理商: CY7C1168V18-300BZXI
CY7C1166V18
CY7C1177V18
CY7C1168V18
CY7C1170V18
Document Number: 001-06620 Rev. *C
Page 15 of 27
TAP Controller Block Diagram
Figure 3. Tap Controller Block Diagram
TAP Electrical Characteristics
The Tap Electrical Characteristics table over the operating range follows.
[10, 11, 12]
Parameter
Description
Test Conditions
Min
Max
Unit
V
OH1
Output HIGH Voltage
I
OH
=
2.0 mA
I
OH
=
100
μ
A
1.4
V
V
OH2
Output HIGH Voltage
1.6
V
V
OL1
Output LOW Voltage
I
OL
= 2.0 mA
I
OL
= 100
μ
A
0.4
V
V
OL2
Output LOW Voltage
0.2
V
V
IH
Input HIGH Voltage
0.65 V
DD
V
DD
+ 0.3
V
V
IL
Input LOW Voltage
–0.3
0.35 V
DD
V
I
X
Input and Output Load Current
GND
V
I
V
DD
5
5
μ
A
0
0
1
2
.
.
29
30
31
Boundary Scan Register
Identification Register
0
1
2
.
.
.
.
106
0
1
2
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI
TDO
TCK
TMS
Notes
10.These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
11. Overshoot: V
(AC) < V
+ 0.35V (pulse width less than t
CYC
/2), undershoot: V
IL
(AC) >
0.3V (pulse width less than t
CYC
/2).
12.All voltage refer to ground.
[+] Feedback
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