參數(shù)資料
型號(hào)： CY7C1166V18-333BZI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
中文描述： 2M X 8 DDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁數(shù)： 17/27頁
文件大?。?/td> 963K
代理商： CY7C1166V18-333BZI
CY7C1166V18
CY7C1177V18
CY7C1168V18
CY7C1170V18
Document Number: 001-06620 Rev. *C
Page 17 of 27
Identification Register Definitions
Instruction Field
Value
Description
CY7C1166V18
000
CY7C1177V18
000
CY7C1168V18
000
CY7C1170V18
000
Revision Number
(31:29)
Cypress Device ID
(28:12)
Cypress JEDEC ID
(11:1)
Version number.
11010111000000101
11010111000001101
11010111000010101
11010111000100101 Defines the type of
SRAM.
Allows unique
identification of
SRAM vendor.
Indicates the
presence of an ID
register.
00000110100
00000110100
00000110100
00000110100
ID Register
Presence (0)
1
1
1
1
Scan Register Sizes
Register Name
Bit Size
3
1
32
107
Instruction
Bypass
ID
Boundary Scan
Instruction Codes
Instruction
Code
000
001
Description
EXTEST
IDCODE
Captures the input output ring contents.
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
Captures the Input Output contents. It places the boundary scan register between
TDI and TDO. This forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the input output ring contents. It places the boundary scan register between
TDI and TDO. This operation does not affect the SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect
SRAM operation.
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
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相關(guān)PDF資料
PDF描述
CY7C1166V18-333BZXC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1166V18-333BZXI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1168V18 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1168V18-300BZC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1168V18-300BZI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C11681KV18-400BZC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mb x 18 400 MHz Sync 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C11681KV18-400BZXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mb x 18 400 MHz Sync 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C11681KV18-450BZC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mb x 18 450 MHz Sync 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C11681KV18-450BZXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mb x 18 450 MHz Sync 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1168KV18-400BZC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18MB (1Mx18) 1.8v 400MHz DDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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