參數(shù)資料
型號: CY7C1166V18-300BZXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
中文描述: 2M X 8 DDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁數(shù): 16/27頁
文件大小: 963K
代理商: CY7C1166V18-300BZXC
CY7C1166V18
CY7C1177V18
CY7C1168V18
CY7C1170V18
Document Number: 001-06620 Rev. *C
Page 16 of 27
TAP AC Switching Characteristics
The Tap AC Switching Characteristics over the operating range follows.
[13, 14]
Parameter
t
TCYC
t
TF
t
TH
t
TL
Setup Times
t
TMSS
t
TDIS
t
CS
Hold Times
t
TMSH
t
TDIH
t
CH
Output Times
t
TDOV
t
TDOX
Description
Min
50
Max
Unit
ns
MHz
ns
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
TCK Clock LOW
20
20
20
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
ns
ns
ns
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
5
5
5
ns
ns
ns
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
10
ns
ns
0
TAP Timing and Test Condition
The Tap Timing and Test Conditions for the CY7C1166V18, CY7C1177V18, CY7C1168V18, and CY7C1170V18 follows.
[14]
Figure 4. TAP Timing and Test Conditions
t
TL
t
TH
(a)
TDO
C
L
= 20 pF
Z
0
= 50
GND
0.9V
50
1.8V
0V
ALL INPUT PULSES
0.9V
Test Clock
TCK
Test Mode Select
TMS
Test Data In
TDI
Test Data Out
TDO
t
TCYC
t
TMSH
t
TMSS
t
TDIS
t
TDIH
t
TDOV
t
TDOX
Notes
13.t
and t
refer to the setup and hold time requirements of latching data from the boundary scan register.
14.Test conditions are specified using the load in TAP AC test conditions. t
R
/t
F
= 1 ns
[+] Feedback
相關PDF資料
PDF描述
CY7C1166V18-300BZXI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1166V18-333BZC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1166V18-333BZI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1166V18-333BZXC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1166V18-333BZXI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
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