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參數(shù)資料
| 型號(hào)： | CY7C1163V18-333BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| 中文描述： | 1M X 18 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FPBGA-165 |
| 文件頁(yè)數(shù)： | 7/29頁(yè) |
| 文件大小： | 956K |
| 代理商： | CY7C1163V18-333BZXC |
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CY7C1161V18
CY7C1176V18
CY7C1163V18
CY7C1165V18
Document Number: 001-06582 Rev. *C
Page 7 of 29
CQ
Echo Clock
Synchronous Echo Clock Outputs
. This is a free running clock and is synchronized to the input
clock (K) of the QDR-II+. The timings for the echo clocks are shown in
“Switching Characteristics”
on page 23.
ZQ
Input
Output Impedance Matching Input
. Used to tune the device outputs to the system data bus
impedance. CQ, CQ and Q
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin is connected directly to V
DDQ
, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left uncon-
nected.
DOFF
Input
DLL Turn Off
Active LOW
. Connecting this pin to ground turns off the DLL inside the device. The
timings in the DLL turned-off operation are different from those listed in this data sheet. For normal
operation, this pin is connected to a pull up through a 10 K
or less pull up resistor. The device
behaves in QDR-I mode when the DLL is turned off. In this mode, the device operates at a frequency
of up to 167 MHz with QDR-I timing.
TDO
Output
TDO for JTAG
.
TCK
Input
TCK pin for JTAG
.
TDI
Input
TDI pin for JTAG
.
TMS
Input
TMS pin for JTAG
.
NC
N/A
Not connected to the die
. Can be tied to any voltage level.
NC/36M
N/A
Not connected to the die
. Can be tied to any voltage level.
NC/72M
N/A
Not connected to the die
. Can be tied to any voltage level.
NC
/144M
N/A
Not connected to the die
. Can be tied to any voltage level.
NC
/288M
N/A
Not connected to the die
. Can be tied to any voltage level.
V
REF
Input-
Reference
Reference Voltage Input
. Static input used to set the reference level for HSTL inputs, outputs, and
AC measurement points.
V
DD
Power Supply
Power supply inputs to the core of the device
.
V
SS
Ground
Ground for the device
.
V
DDQ
Power Supply
Power supply inputs for the outputs of the device
.
Pin Definitions
(continued)
Pin Name
IO
Pin Description
[+] Feedback
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| CY7C1163V18-333BZXI | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1165V18 | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1165V18-300BZC | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1165V18-300BZI | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1165V18-300BZXC | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
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| CY7C11651KV18-400BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 Sync 靜態(tài)隨機(jī)存取存儲(chǔ)器 QDR RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C11651KV18-400BZXC | 功能描述:IC SRAM 18MBIT 400MHZ 165-FPBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁(yè)面:1445 (CN2011-ZH PDF) |
| CY7C1165AC | 制造商:Cypress Semiconductor 功能描述: |
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