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參數(shù)資料
| 型號(hào)： | CY7C1161V18-333BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| 中文描述： | 2M X 8 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FPBGA-165 |
| 文件頁數(shù)： | 11/29頁 |
| 文件大小： | 956K |
| 代理商： | CY7C1161V18-333BZXC |
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CY7C1161V18
CY7C1176V18
CY7C1163V18
CY7C1165V18
Document Number: 001-06582 Rev. *C
Page 11 of 29
Write Cycle Descriptions
The write cycle descriptions of CY7C1161V18 and CY7C1163V18 follow.
[3, 11]
BWS
0
/
NWS
0
BWS
1
/
NWS
1
K
K
Comments
L
L
L–H
–
During the data portion of a write sequence
:
CY7C1161V18
both nibbles (D
[7:0]
) are written into the device.
CY7C1163V18
both bytes (D
[17:0]
) are written into the device.
L-H During the data portion of a write sequence
:
CY7C1161V18
both nibbles (D
[7:0]
) are written into the device.
CY7C1163V18
both bytes (D
[17:0]
) are written into the device.
During the data portion of a write sequence
:
CY7C1161V18
only the lower nibble (D
[3:0]
) is written into the device, D
[7:4]
remains unaltered.
CY7C1163V18
only the lower byte (D
[8:0]
) is written into the device, D
[17:9]
remains unaltered.
L–H During the data portion of a write sequence
:
CY7C1161V18
only the lower nibble (D
[3:0]
) is written into the device, D
[7:4]
remains unaltered.
CY7C1163V18
only the lower byte (D
[8:0]
) is written into the device, D
[17:9]
remains unaltered.
During the data portion of a write sequence
:
CY7C1161V18
only the upper nibble (D
[7:4]
) is written into the device, D
[3:0]
remains unaltered.
CY7C1163V18
only the upper byte (D
[17:9]
) is written into the device, D
[8:0]
remains unaltered.
L–H During the data portion of a write sequence
:
CY7C1161V18
only the upper nibble (D
[7:4]
) is written into the device, D
[3:0]
remains unaltered.
CY7C1163V18
only the upper byte (D
[17:9]
) is written into the device, D
[8:0]
remains unaltered.
L
L
–
L
H
L–H
–
L
H
–
H
L
L–H
–
H
L
–
H
H
L–H
–
No data is written into the device during this portion of a write operation.
H
H
–
L–H No data is written into the device during this portion of a write operation.
The write cycle operation of CY7C1176V18 follows.
[3, 11]
BWS
0
K
K
L
L–H
–
During the data portion of a write sequence, the single byte (D
[8:0]
) is written into the device.
L
–
L–H
During the data portion of a write sequence, the single byte (D
[8:0]
) is written into the device.
H
L–H
–
No data is written into the device during this portion of a write operation.
H
–
L–H
No data is written into the device during this portion of a write operation.
Note
11. Is based upon a Write cycle was initiated per the Write Cycle Description Truth Table. NWS
0
, NWS
1
,
BWS
0
, BWS
1
, BWS
2
,
and BWS
3
can be altered on different
portions of a Write cycle, as long as the setup and hold requirements are achieved.
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1161V18-333BZXI | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1163V18 | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1163V18-300BZC | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1163V18-300BZI | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1163V18-300BZXC | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
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