參數(shù)資料
型號： CY7C1150V18
廠商： Cypress Semiconductor Corp.
英文描述： 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
中文描述： 18兆位的DDR - II SRAM的2字突發(fā)架構（2.0周期讀寫延遲）
文件頁數(shù)： 22/27頁
文件大?。?/td> 969K
代理商： CY7C1150V18
CY7C1146V18
CY7C1157V18
CY7C1148V18
CY7C1150V18
Document Number: 001-06621 Rev. *C
Page 22 of 27
Switching Characteristics
Over the operating range
[20, 21]
Cypress
Parameter
Consortium
Parameter
Description
375 MHz
Min
1
2.66 8.40
0.425
0.425
1.13
333 MHz
Min
1
3.0
0.425
0.425
1.28
300 MHz
Min
1
3.3
0.425
0.425
1.40
Unit
Max
–
Max
–
8.40
–
–
–
Max
–
8.40
–
–
–
t
POWER
t
CYC
t
KH
t
KL
t
KHKH
Setup Times
t
SA
t
SC
t
SCDDR
V
DD
(Typical) to the first Access
[22]
K Clock Cycle Time
Input Clock (K/K) HIGH
Input Clock (K/K) LOW
K Clock Rise to K Clock Rise (rising edge to rising edge)
ms
ns
t
CYC
t
CYC
ns
t
KHKH
t
KHKL
t
KLKH
t
KHKH
–
–
–
t
AVKH
t
IVKH
t
IVKH
Address Setup to K Clock Rise
Control Setup to K Clock Rise (LD, R/W)
Double Data Rate Control Setup to Clock (K/K) Rise (BWS
0
,
BWS
1
, BWS
2
, BWS
3
)
D
[X:0]
Setup to Clock (K/K) Rise
0.4
0.4
0.28
–
–
–
0.4
0.4
0.28
–
–
–
0.4
0.4
0.28
–
–
–
ns
ns
ns
t
SD
Hold Times
t
HA
t
HC
t
HCDDR
t
DVKH
0.28
–
0.28
–
0.28
–
ns
t
KHAX
t
KHIX
t
KHIX
Address Hold after K Clock Rise
Control Hold after K Clock Rise (LD, R/W)
Double Data Rate Control Hold after Clock (K/K) Rise (BWS
0
,
BWS
1
, BWS
2
, BWS
3
)
D
[X:0]
Hold after Clock (K/K) Rise
0.4
0.4
0.28
–
–
–
0.4
0.4
0.28
–
–
–
0.4
0.4
0.28
–
–
–
ns
ns
ns
t
HD
Output Times
t
CO
t
DOH
t
CCQO
t
CQOH
t
CQD
t
CQDOH
t
CQH
t
CQHCQH
t
KHDX
0.28
–
0.28
–
0.28
–
ns
t
CHQV
t
CHQX
t
CHCQV
t
CHCQX
t
CQHQV
t
CQHQX
t
CQHCQL
t
CQHCQH
K/K Clock Rise to Data Valid
Data Output Hold after K/K Clock Rise (Active to Active)
K/K Clock Rise to Echo Clock Valid
Echo Clock Hold after K/K Clock Rise
Echo Clock High to Data Valid
Echo Clock High to Data Invalid
Output Clock (CQ/CQ) HIGH
[23]
CQ Clock Rise to CQ Clock Rise
[23]
(rising edge to rising edge)
Clock (K/K) Rise to High-Z (Active to High-Z)
[24, 25]
Clock (K/K) Rise to Low-Z
[24, 25]
Echo Clock High to QVLD Valid
[26]
–
0.45
–
0.45
–
0.2
–
–
–
–
0.45
–
0.45
–
0.2
–
–
–
–
0.45
–
0.45
–
0.2
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
–0.45
–
–0.45
–
–0.2
0.88
0.88
–0.45
–
–0.45
–
–0.2
1.03
1.03
–0.45
–
–0.45
–
–0.2
1.15
1.15
t
CHZ
t
CLZ
t
QVLD
DLL Timing
t
KC Var
t
KC lock
t
KC Reset
t
CHQZ
t
CHQX1
t
QVLD
–
0.45
–
–
0.45
–
–
0.45
–
ns
ns
ns
–0.45
–0.20 0.20 –0.20 0.20 –0.20 0.20
–0.45
–0.45
t
KC Var
t
KC lock
t
KC Reset
Clock Phase Jitter
DLL Lock Time (K)
K Static to DLL Reset
[27]
–
0.20
–
–
–
0.20
–
–
–
0.20
–
–
ns
2048
30
2048
30
2048
30
Cycles
ns
Notes
21.When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
22.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
minimum initially before a read or write operation can
be initiated.
23.These parameters are extrapolated from the input timing parameters (t
– 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t
KC Var
) is already
included in the t
KHKH
). These parameters are only guaranteed by design and are not tested in production.
24.t
CHZ
, t
CLZ
, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
±
100 mV from steady-state voltage.
25.At any voltage and temperature t
CHZ
is less than t
CLZ
and t
CHZ
less than t
CO
.
26.t
QVLD
spec is applicable for both rising and falling edges of QVLD signal.
27.Hold to >V
IH
or <V
IL
.
[+] Feedback
相關PDF資料
PDF描述
CY7C1150V18-333BZC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-333BZI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1156V18-300BZXI 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1141V18 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
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