參數(shù)資料
型號: CY7C1145V18-300BZXI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
中文描述: 512K X 36 QDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FPBGA-165
文件頁數(shù): 24/28頁
文件大?。?/td> 954K
代理商: CY7C1145V18-300BZXI
CY7C1141V18
CY7C1156V18
CY7C1143V18
CY7C1145V18
Document Number: 001-06583 Rev. *C
Page 24 of 28
Switching Waveforms
Read/Write/Deselect Sequence
Figure 7. Waveform for 2.0 Cycle Read Latency
[29, 30, 31]
tKH
tKL
tCYC
tKHKH
NOP
6
READ
2
NOP
1
WRITE
3
READ
4
WRITE
5
7
8
t
t
t
tSA
HA
SC
HC
tHD
tSC
tHC
A0
A1
A2
A3
t
t
SD
HD
tSD
D11
D10
D12
D13
D30
D31
D32
D33
D
A
WPS
RPS
K
K
DON’T CARE
UNDEFINED
CQ
CQ
tCQOH
CCQO
t
tCQOH
CCQO
t
tQVLD
QVLD
tQVLD
(Read Latency = 2.0 Cycles)
CLZ
t
t
CO
tDOH
tCQDOH
CQD
t
tCHZ
Q00
Q01
Q20
Q02
Q21
Q03
Q22
Q23
tCQH
t
CQHCQH
Q
Notes
29.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.
30.Outputs are disabled (High-Z) one clock cycle after a NOP.
31.In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
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相關(guān)PDF資料
PDF描述
CY7C1156V18 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1156V18-300BZC 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1156V18-300BZI 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1156V18-300BZXC 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1223F-133AC 2-Mb (128K x 18) Pipelined DCD Sync SRAM
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