參數(shù)資料
型號: CY7C1049V33
廠商: Cypress Semiconductor Corp.
英文描述: 512K x 8 Static RAM(512K x 8 靜態(tài)RAM)
中文描述: 為512k × 8靜態(tài)存儲器(為512k × 8靜態(tài)RAM)的
文件頁數(shù): 1/8頁
文件大?。?/td> 124K
代理商: CY7C1049V33
512K x 8 Static RAM
CY7C1049V33
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
June 2, 1999
3
Features
High speed
—t
AA
= 15 ns
Low active power
—504 mW (max.)
Low CMOS standby power (Commercial L version)
—1.8 mW (max.)
2.0V Data Retention (660
μ
W at 2.0V retention)
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
Functional Description
The CY7C1049V33 is a high-performance CMOS Static RAM
organized as 524,288 words by 8 bits. Easy memory expan-
sion is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and three-state drivers. Writing to
the device is accomplished by taking Chip Enable (CE) and
Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O
0
through I/O
7
) is then written into the location specified on the
address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049V33 is available in a standard 400-mil-wide
36-pin SOJ package with center power and ground (revolution-
ary) pinout.
Pin Configuration
1
A
1
A
Logic Block Diagram
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
COLUMN
DECODER
R
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
512K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
A
1
A
1
CE
A
1
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
23
22
24
28
27
26
25
29
32
31
30
Top View
SOJ
33
36
35
34
16
17
21
20
GND
I/O
2
I/O3
A
1
A
2
A
3
A
4
CE
A
5
A
6
A
7
A
8
A
9
WE
V
CC
I/O
5
I/O
4
A
18
A
17
A
16
A
15
OE
I/O
7
I/O
6
A
12
A
11
A
14
A
13
1049V33–1
A
0
I/O
0
I/O
1
V
CC
1049V33–2
A
1
18
19
GND
A
10
NC
NC
Selection Guide
1049V33-12
12
150
8
0.5
1049V33-15
15
140
8
0.5
1049V33-17
17
130
8
0.5
1049V33-20
20
120
8
0.5
1049V33-25
25
110
8
0.5
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby
Current (mA)
Com’l/Ind’l
Com’l
L
Shaded areas contain preliminary information.
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