參數(shù)資料
型號: CY7C1069DV33
廠商: Cypress Semiconductor Corp.
英文描述: 16-Mbit (2M x 8) Static RAM
中文描述: 16兆位(2米× 8)靜態(tài)RAM
文件頁數(shù): 1/9頁
文件大?。?/td> 382K
代理商: CY7C1069DV33
PRELIMINARY
16-Mbit (2M x 8) Static RAM
CY7C1069DV33
Cypress Semiconductor Corporation
Document #: 38-05478 Rev. *C
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised September 14, 2006
Features
High speed
— t
AA
= 10 ns
Low active power
— I
CC
= 125 mA @ 10 ns
Low CMOS standby power
— I
SB2
= 25 mA
Operating voltages of 3.3 ± 0.3V
2.0V data retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE
1
and CE
2
features
Available in Pb-free 54-pin TSOP II package and 48-ball
VFBGA packages
Functional Description
The CY7C1069DV33 is a high-performance CMOS Static
RAM organized as 2,097,152 words by 8 bits. Writing to the
device is accomplished by enabling the chip (by taking CE
1
LOW and CE
2
HIGH) and Write Enable (WE) inputs LOW.
Reading from the device is accomplished by enabling the chip
(CE
1
LOW and CE
2
HIGH) as well as forcing the Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
See the truth table at the back of this data sheet for a complete
description of Read and Write modes.
The input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a Write operation (CE
1
LOW, CE
2
HIGH, and WE
LOW).
The CY7C1069DV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and a
48-ball very fine-pitch ball grid array (VFBGA) package.
Selection Guide
–10
10
125
25
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Logic Block Diagram
Pin Configuration
Top View
TSOP II
WE
CE
2
A
19
A
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
30
32
36
35
34
33
37
40
39
38
41
43
42
16
17
29
28
A
5
A
6
A
7
A
8
A
9
NC
A
0
NC
A
1
OE
V
SS
V
SS
I/O
7
A
4
A
17
A
16
A
15
A
2
CE
1
V
I/O
0
V
CC
I/O
1
NC
A
3
18
19
20
21
27
25
26
22
23
24
I/O
2
NC
I/O
3
V
V
CC
NC
I/O
6
NC
I/O
5
V
CC
I/O
4
A
14
A
13
A
12
A
11
A
10
44
46
45
47
50
49
48
51
53
52
54
V
SS
NC
V
CC
NC
NC
A
20
V
NC
NC
1
A
1
A
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
COLUMN
DECODER
R
S
INPUT BUFFER
2M x 8
ARRAY
A
0
A
1
A
1
A
1
A
1
A
1
A
1
A
1
I/O
0
–I/O
7
OE
CE
2
WE
CE
1
A
1
A
2
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