參數(shù)資料
型號(hào): CY7C1049BV33L-15VC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 512K x 8 Static RAM
中文描述: 512K X 8 STANDARD SRAM, 15 ns, PDSO36
封裝: 0.400 INCH, PLASTIC, SOJ-36
文件頁數(shù): 5/10頁
文件大?。?/td> 165K
代理商: CY7C1049BV33L-15VC
CY7C1049BV33
Document #: 38-05139 Rev. *A
Page 5 of 10
AC Switching Characteristics
[4]
Over the Operating Range (continued)
Parameter
Read Cycle
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[9]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Description
-20
-25
Unit
Min.
Max.
Min.
Max.
V
CC
(typical) to the First Access
[6]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[6, 7]
CE LOW to Low Z
[7]
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
1
1
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
25
20
25
3
3
20
8
25
10
0
0
8
10
3
3
8
10
0
0
20
25
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[7]
WE LOW to High Z
[6, 7]
20
13
13
0
0
13
9
0
3
25
15
15
0
0
15
10
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
10
Data Retention Characteristics
Over the Operating Range (For L version only)
Parameter
Description
Conditions
[10]
Min.
2.0
Max
Unit
V
μ
A
ns
V
DR
I
CCDR
t
CDR[3]
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention
Time
Operation Recovery Time
V
CC
= V
DR
= 2.0V,
CE > V
CC
0.3V
V
IN
> V
CC
0.3V or V
IN
< 0.3V
330
0
t
R[11]
Notes:
10. No input may exceed V
+ 0.5V
11.
.t
r
< 3 ns for the -12 and -15 speeds. t
r
< 5 ns for the -20 ns and slower speeds.
t
RC
ns
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