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參數(shù)資料
| 型號： | CY7C1046DV33 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4-Mbit (1M x 4) Static RAM |
| 中文描述： | 4兆位（1米× 4）靜態(tài)RAM |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 389K |
| 代理商： | CY7C1046DV33 |
4-Mbit (1M x 4) Static RAM
CY7C1046DV33
Cypress Semiconductor Corporation
Document #: 38-05611 Rev. *B
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised April 3, 2006
Features
Pin- and function-compatible with CY7C1046CV33
High speed
— t
AA
= 10 ns
Low active power
— I
CC
= 90 mA @ 10 ns
Low CMOS standby power
— I
SB2
= 10 mA
2.0 V data retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
Available in lead-free 400-mil-wide 32-pin SOJ package
Functional Description
[1]
The CY7C1046DV33 is a high-performance CMOS static
RAM organized as 1M words by 4 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. Writing
to the device is accomplished by taking Chip Enable (CE) and
Write Enable (WE) inputs LOW. Data on the four I/O pins (I/O
0
through I/O
3
) is then written into the location specified on the
address pins (A
0
through A
19
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The four input/output pins (I/O
0
through I/O
3
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
The CY7C1046DV33 is available in a standard 400-mil-wide
32-pin SOJ package with center power and ground (revolu-
tionary) pinout.
Pin Configuration
Selection Guide
1
A
1
A
Logic Block Diagram
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
COLUMN
DECODER
R
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
1 Mbit x 4
I/O
3
I/O
2
A
0
A
1
A
1
A
1
CE
A
1
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
21
20
22
25
24
23
28
27
26
Top View
SOJ
29
32
31
30
14
15
19
18
GND
I/O
1
A
1
A
2
A
3
A
4
CE
A
5
A
6
A
7
A
8
A
9
WE
V
CC
I/O
2
A
18
A
17
A
16
A
15
OE
I/O
3
A
12
A
11
A
14
A
13
A
0
I/O
0
V
CC
A
1
16
17
GND
A
10
NC
A
19
A
1
-10
10
90
10
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Note:
1. For guidelines on SRAM system design, please refer to the
System Design Guidelines
Cypress application note, available on the internet at www.cypress.com.
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