參數(shù)資料
型號(hào): CY7C1046V33
廠商: Cypress Semiconductor Corp.
英文描述: 1M x 4 Static RAM(4M靜態(tài)RAM)
中文描述: 100萬× 4靜態(tài)存儲(chǔ)器(4分靜態(tài)RAM)的
文件頁數(shù): 1/7頁
文件大?。?/td> 130K
代理商: CY7C1046V33
ADVANCE INFORMATION
1M x 4 Static RAM
CY7C1046V33
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
June 4, 1999
3
Features
High speed
—t
AA
= 10 ns
Low active power for 10 ns speed
—540 mW (max.)
Low CMOS standby power (L version)
—1.8 mW (max.)
2.0V Data Retention (400
μ
W at 2.0V retention)
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
Functional Description
The CY7C1046V33 is a high-performance CMOS static RAM
organized as 1,048,576 words by 4 bits. Easy memory expan-
sion is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and three-state drivers. Writing to
the device is accomplished by taking Chip Enable (CE) and
Write Enable (WE) inputs LOW. Data on the four I/O pins (I/O
0
through I/O
3
) is then written into the location specified on the
address pins (A
0
through A
19
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The four input/output pins (I/O
0
through I/O
3
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1046V33 is available in a standard 400-mil-wide
32-pin SOJ package with center power and ground (revolution-
ary) pinout.
Pin Configuration
1
A
1
A
Logic Block Diagram
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
COLUMN
DECODER
R
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
1M x 4
ARRAY
I/O
3
I/O
2
A
0
A
1
A
1
A
1
CE
A
1
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
21
20
22
25
24
23
28
27
26
Top View
SOJ
29
32
31
30
14
15
19
18
GND
I/O
1
A
1
A
2
A
3
A
4
CE
A
5
A
6
A
7
A
8
A
9
WE
V
CC
I/O
2
A
18
A
17
A
16
A
15
OE
I/O
3
A
12
A
11
A
14
A
13
1046V33–1
A
0
I/O
0
V
CC
1046V33–2
A
1
16
17
GND
A
10
NC
A
19
A
1
Selection Guide
7C1046V33-10
10
150
8
0.5
7C1046V33-12
12
140
8
0.5
7C1046V33-15
15
130
8
0.5
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby
Current (mA)
Com’l
L version
Shaded areas contain pre-release information.
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