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參數(shù)資料
| 型號： | CY7C1021CV26 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 1-Mbit (64K x 16) Static RAM |
| 中文描述： | 1兆位（64K的× 16）靜態(tài)RAM |
| 文件頁數(shù)： | 4/9頁 |
| 文件大小： | 247K |
| 代理商： | CY7C1021CV26 |
CY7C1021CV26
Document #: 38-05589 Rev. **
Page 4 of 9
AC Test Loads and Waveforms
[6]
R1
1830
Switching Characteristics
Over the Operating Range
[7]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU[10]
t
PD[10]
t
DBE
t
LZBE
t
HZBE
Write Cycle
[11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
Notes:
6. AC characteristics (except High-Z) are tested using the Thevenin load shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
7. Test conditions assume signal transition time of 2.6 ns or less, timing reference levels of 1.3V, input pulse levels of 0 to 2.6V.
8. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
9. t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
10.This parameter is guaranteed by design and is not tested.
11. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write,
and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
Description
CY7C1021CV26-15
Min.
Unit
Max.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[8]
OE HIGH to High-Z
[8, 9]
CE LOW to Low-Z
[8]
CE HIGH to High-Z
[8, 9]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
3
15
7
0
7
3
7
0
15
7
0
7
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
15
10
10
0
0
10
8
0
ns
ns
ns
ns
ns
ns
ns
ns
2.6 V
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
1976
2.6V
OUTPUT
5 pF
R 317
R2
351
High-Z characteristics:
90%
10%
2.6V
GND
90%
10%
ALL INPUT PULSES
Rise Time: 1 V/ns
Fall Time: 1 V/ns
(c)
(b)
(a)
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| CY7C1021CV26-15ZE | 1-Mbit (64K x 16) Static RAM |
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| CY7C1021CV33-10VXC | 1-Mbit (64K x 16) Static RAM |
| CY7C1021CV33-10ZXC | 1-Mbit (64K x 16) Static RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1021CV26-15BAE | 功能描述:靜態(tài)隨機(jī)存取存儲器 64K X 16 2.6V RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1021CV26-15BAET | 功能描述:靜態(tài)隨機(jī)存取存儲器 64K X 16 2.6V RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1021CV26-15VXE | 功能描述:靜態(tài)隨機(jī)存取存儲器 64K X 16 2.6V RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1021CV26-15VXET | 功能描述:靜態(tài)隨機(jī)存取存儲器 64K X 16 2.6V RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1021CV26-15XEKJ | 制造商:Cypress Semiconductor 功能描述: |
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