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參數(shù)資料
| 型號： | CY7C1021BNV33L-15ZXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 64K x 16 Static RAM |
| 中文描述： | 64K X 16 STANDARD SRAM, 15 ns, PDSO44 |
| 封裝： | LEAD FREE, TSOP2-44 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 530K |
| 代理商： | CY7C1021BNV33L-15ZXI |
64K x 16 Static RAM
Functional Description
[1]
CY7C1021BNV33
Cypress Semiconductor Corporation
Document #: 001-06433 Rev. **
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised February 1, 2006
Features
3.3V operation (3.0V–3.6V)
High speed
— t
AA
= 10, 12, 15 ns
CMOS for optimum speed/power
Low Active Power (L version)
— 576 mW (max.)
Low CMOS Standby Power (L version)
— 1.80 mW (max.)
Automatic power-down when deselected
Independent control of upper and lower bits
Available in 44-pin TSOP II and 400-mil SOJ
Available in a 48-Ball Mini BGA package
The CY7C1021BNV is a high-performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
1
through I/O
8
), is
written into the location specified on the address pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
9
through I/O
16
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
1
to I/O
8
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
9
to I/O
16
.
See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
1
through I/O
16
) are placed in a
high-impedance state when the device is deselected
(CE HIGH), the outputs are disabled (OE HIGH), the BHE and
BLE are disabled (BHE, BLE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1021BNV is available in 400-mil-wide SOJ,
standard 44-pin TSOP Type II, and 48-ball mini BGA
packages.
WE
A15
A14
A13
A12
NC
Logic Block Diagram
Pin Configurations
SOJ / TSOP II
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
30
32
36
35
34
33
37
40
39
38
Top View
41
44
43
42
16
17
29
28
CC
V
I/O5
I/O6
A
4
A3
A2
A1
A0
OE
BHE
BLE
SS
V
I/O12
I/O11
I/O10
I/O9
A5
A6
A7
I/O16
I/O15
I/O14
V
CE
I/O1
I/O2
I/O3
V
NC
A8
A9
A10
A11
18
19
20
21
27
26
25
24
22
23
NC
I/O7
64K x 16
RAM Array
512 X 2048
I/O
1
–I/O
8
R
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
COLUMN DECODER
A
9
A
1
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
BLE
I/O
9
–I/O
16
OE
WE
A
8
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1021BNV33L-15ZXIT | 功能描述:靜態(tài)隨機存取存儲器 64K x 16 ASYNC 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1021BV3310BAC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1021BV33-10BACT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 1M-Bit 64K x 16 10ns 48-Pin FBGA T/R |
| CY7C1021BV33-10VC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1021BV33-10ZC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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