參數(shù)資料
型號: CY7C1009B-20VXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 128K X 8 STANDARD SRAM, 20 ns, PDSO32
封裝: 0.300 INCH, LEAD FREE, SOJ-32
文件頁數(shù): 5/10頁
文件大?。?/td> 362K
代理商: CY7C1009B-20VXC
CY7C109B
CY7C1009B
Document #: 38-05038 Rev. *C
Page 4 of 10
Data Retention Characteristics Over the Operating Range (Low Power version only)
Parameter
Description
Conditions
Min.
Max.
Unit
VDR
VCC for Data Retention
No input may exceed VCC + 0.5V
VCC = VDR = 2.0V,
CE1 > VCC – 0.3V or CE2 < 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
2.0
V
ICCDR
Data Retention Current
150
A
tCDR
Chip Deselect to Data Retention Time
0
ns
tR
Operation Recovery Time
200
s
Data Retention Waveform
Switching Waveforms
Read Cycle No. 1[10, 11]
Read Cycle No. 2 (OE Controlled)[11, 12]
Notes:
10. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
4.5V
CE
VCC
tCDR
VDR > 2V
DATA RETENTION MODE
tR
PREVIOUS DATA VALID
DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
HIGH
OE
CE1
ICC
ISB
IMPEDANCE
ADDRESS
CE2
DATA OUT
VCC
SUPPLY
CURRENT
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