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參數(shù)資料
| 型號： | CY7C09389-7AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 32K/64K X 16/18 Synchronous Dual Port Static RAM |
| 中文描述： | 64K X 18 DUAL-PORT SRAM, 18 ns, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 342K |
| 代理商： | CY7C09389-7AC |
CY7C09279/89
CY7C09379/89
Document #: 38-06040 Rev. **
Page 7 of 18
Notes:
12. Test conditions used are Load 2.
13. This parameter is guaranteed by design, but it is not production tested.
Switching Characteristics
Over the Operating Range
Parameter
f
MAX1
f
MAX2
t
CYC1
t
CYC2
t
CH1
t
CL1
t
CH2
t
CL2
t
R
t
F
t
SA
t
HA
t
SC
t
HC
t
SW
t
HW
t
SD
t
HD
t
SAD
t
HAD
t
SCN
t
HCN
t
SRST
t
HRST
t
OE
t
OLZ[12, 13]
t
OZ[12, 13]
t
CD1
t
CD2
t
DC
t
CKHZ[12, 13]
t
CKLZ[12, 13]
Port to Port Delays
t
CWDD
t
CCS
Description
CY7C09279/89
CY7C09379/89
-7
Max.
45
83
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-6
[1]
-9
-12
Min.
Max.
53
100
Min.
Min.
Max.
40
67
Min.
Max.
33
50
f
Max
Flow-Through
f
Max
Pipelined
Clock Cycle Time - Flow-Through
Clock Cycle Time - Pipelined
Clock HIGH Time - Flow-Through
Clock LOW Time - Flow-Through
Clock HIGH Time - Pipelined
Clock LOW Time - Pipelined
Clock Rise Time
Clock Fall Time
Address Set-Up Time
Address Hold Time
Chip Enable Set-Up Time
Chip Enable Hold Time
R/W Set-Up Time
R/W Hold Time
Input Data Set-Up Time
Input Data Hold Time
ADS Set-Up Time
ADS Hold Time
CNTEN Set-Up Time
CNTEN Hold Time
CNTRST Set-Up Time
CNTRST Hold Time
Output Enable to Data Valid
OE to Low Z
OE to High Z
Clock to Data Valid - Flow-Through
Clock to Data Valid - Pipelined
Data Output Hold After Clock HIGH
Clock HIGH to Output High Z
Clock HIGH to Output Low Z
19
10
6.5
6.5
4
4
22
12
7.5
7.5
5
5
25
15
12
12
6
6
30
20
12
12
8
8
3
3
3
3
3
3
3
3
3.5
0
3.5
0
3.5
0
3.5
0
3.5
0
3.5
0
3.5
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
1
8
9
10
12
2
1
2
1
2
1
2
1
7
15
6.5
7
18
7.5
7
20
9
7
25
12
2
2
2
2
2
2
2
2
2
2
2
9
9
9
9
Write Port Clock HIGH to Read Data Delay
Clock to Clock Set-Up Time
30
9
35
10
40
15
40
15
ns
ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C09389V-12AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 1.125M-Bit 64K x 18 25ns/12ns 100-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:64KX18 3.3V DUAL PORT SRAM - Bulk |
| CY7C09389V-12ACT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C09389V-12AXC | 功能描述:靜態(tài)隨機存取存儲器 3.3V 32Kx18 COM Sync Dual Port 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C09389V-12AXCT | 功能描述:IC SRAM 1.152MBIT 12NS 100LQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C09389V-6AC | 制造商:Rochester Electronics LLC 功能描述:64KX18 3.3V DUAL PORT SRAM - Bulk |
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