參數(shù)資料
型號: CY7C09199V-9AXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
中文描述: 128K X 9 DUAL-PORT SRAM, 20 ns, PQFP100
封裝: ROHS COMPLIANT, PLASTIC, MS-026, TQFP-100
文件頁數(shù): 9/28頁
文件大?。?/td> 657K
代理商: CY7C09199V-9AXC
CY7C09089V/99V
CY7C09179V/99V
Document #: 38-06043 Rev. *F
Page 17 of 28
Figure 11. Pipelined Read-to-Write-to-Read (OE Controlled)[37, 38, 39, 40]
Switching Waveforms (continued)
tCYC2
tCL2
tCH2
tHC
tSC
tHW
tSW
tHA
tSA
An
An+1
An+2
An+3
An+4
An+5
tHW
tSW
tSD tHD
Dn+2
tCD2
tOHZ
READ
WRITE
Dn+3
tCKLZ
tCD2
Qn
Qn+4
CLK
CE0
CE1
R/W
ADDRESS
DATAIN
DATAOUT
OE
Notes
37. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
38. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
39. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
40. During “No Operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity.
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