參數(shù)資料
型號(hào)： CY7C09199V-9AXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： SRAM
英文描述： 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
中文描述： 128K X 9 DUAL-PORT SRAM, 20 ns, PQFP100
封裝： ROHS COMPLIANT, PLASTIC, MS-026, TQFP-100
文件頁(yè)數(shù)： 26/28頁(yè)
文件大?。?/td> 657K
代理商： CY7C09199V-9AXC
CY7C09089V/99V
CY7C09179V/99V
Document #: 38-06043 Rev. *F
Page 7 of 28
Selection Guide
Description
CY7C09179V
CY7C09099V
CY7C09199V
-9
CY7C09089V/99V
CY7C09179V
-12
fMAX2 (MHz) (Pipelined)
100
83
67
50
Max. Access Time (ns) (Clock to Data,
Pipelined)
6.5
7.5
9
12
Typical Operating Current ICC (mA)
175
155
135
115
Typical Standby Current for ISB1 (mA)
(Both Ports TTL Level)
25
20
Typical Standby Current for ISB3 (A)
(Both Ports CMOS Level)
10
Pin Definitions
Left Port
Right Port
Description
A0L–A16L
A0R–A16R
Address Inputs (A0–A14 for 32K; A0–A15 for 64K; and A0–A16 for 128K devices).
ADSL
ADSR
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
access the part using an externally supplied address. Asserting this signal LOW also loads
the burst counter with the address present on the address pins.
CE0L, CE1L
CE0R, CE1R
Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted
to their active states (CE0 VIL and CE1 VIH).
CLKL
CLKR
Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX.
CNTENL
CNTENR
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
CNTRSTL
CNTRSTR
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its
respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O0L–I/O8L
I/O0R–I/O8R
Data Bus Input/Output (I/O0–I/O7 for ×8 devices; I/O0–I/O8 for ×9 devices).
OEL
OER
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during
read operations.
R/WL
R/WR
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
FT/PIPEL
FT/PIPER
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
GND
Ground Input.
NC
No Connect.
VCC
Power Input.
Note
10. See page 9 and page 10 for Load Conditions.
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