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參數(shù)資料
| 型號(hào)： | CY7C09169A |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 16K x 9 Synchronous Dual-Port Static RAM(16K x 9 同步雙端口靜態(tài)RAM) |
| 中文描述： | 16K的× 9同步雙端口靜態(tài)存儲(chǔ)器（16K的× 9同步雙端口靜態(tài)RAM）的 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 319K |
| 代理商： | CY7C09169A |
CY7C09159A
CY7C09169A
PRELIMINARY
2
Functional Description
The CY7C09159A and CY7C09169A are high-speed synchro-
nous CMOS 8K and 16K x 9 dual-port static RAMs. Two ports
are provided, permitting independent, simultaneous access for
reads and writes to any location in memory.
[3]
Registers on
control, address, and data lines allow for minimal set-up and
hold times. In pipelined output mode, data is registered for
decreased cycle time. Clock to data valid t
CD2
= 6.5 ns
[1]
(pipe-
lined). Flow-through mode can also be used to bypass the
pipelined output register to eliminate access latency. In flow-
through mode data will be available
t
CD1
= 15 ns
after the ad-
dress is clocked into the device. Pipelined output or flow-
through mode is selected via the FT/Pipe pin.
Each port contains a burst counter on the input address regis-
ter. The internal write pulse width is independent of the LOW-
to-HIGH transition of the clock signal. The internal write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE
0
or LOW on CE
1
for one clock cycle will power
down the internal circuitry to reduce the static power consump-
tion. The use of multiple Chip Enables allows easier banking
of multiple chips for depth expansion configurations. In the
pipelined mode, one cycle is required with CE
0
LOW and CE
1
HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port
’
s burst counter is loaded with the port
’
s Address Strobe
(ADS). When the port
’
s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port
’
s clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST)
is used to reset the burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Note:
3.
When simultaneously writing to the same location, final value cannot be guaranteed.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C09159V | 3.3V 8K x 9 Synchronous Dual-Port Static RAM(3.3V 8K x 9 同步雙端口靜態(tài)RAM) |
| CY7C09169V | 3.3V 16K x 9 Synchronous Dual-Port Static RAM(3.3V 16K x 9 同步雙端口靜態(tài)RAM) |
| CY7C09159 | 8K x 9 Synchronous Dual-Port Static RAM(8K x 9 同步雙端口靜態(tài)RAM) |
| CY7C09179A | 32K x 9 Synchronous Dual-Port Static RAM(32K x 9 同步雙端口靜態(tài)RAM) |
| CY7C09079A | 32K x 8 Synchronous Dual-Port Static RAM(32K x 8 同步雙端口靜態(tài)RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C09169AV-12AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C09169AV-12AI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C09169AV-12AXC | 功能描述:IC SRAM 144KBIT 12NS 100LQFP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C09169AV-12AXI | 功能描述:IC SRAM 144KBIT 12NS 100LQFP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C09179V-12AC | 功能描述:IC SRAM 288KBIT 12NS 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-MSOP 包裝:帶卷 (TR) |
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