參數(shù)資料
型號: CY7C09159
廠商: Cypress Semiconductor Corp.
英文描述: 8K x 9 Synchronous Dual-Port Static RAM(8K x 9 同步雙端口靜態(tài)RAM)
中文描述: 8K的× 9同步雙端口靜態(tài)存儲器(8K的× 9同步雙端口靜態(tài)RAM)的
文件頁數(shù): 4/18頁
文件大?。?/td> 324K
代理商: CY7C09159
CY7C09159
CY7C09169
PRELIMINARY
4
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................
65
°
C to +150
°
C
Ambient Temperature with Power Applied ..
55
°
C to +125
°
C
Supply Voltage to Ground Potential...............
0.3V to +7.0V
DC Voltage Applied to
Outputs in High Z State .................................
0.5V to +7.0V
DC Input Voltage............................................
0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ...........................................>2001V
Latch-Up Current..................................................... >200 mA
Selection Guide
CY7C09159
CY7C09169
-6
[1]
100
6.5
250
45
CY7C09159
CY7C09169
-7
83
7.5
235
40
CY7C09159
CY7C09169
-9
67
9
215
35
CY7C09159
CY7C09169
-12
50
12
195
30
f
MAX2
(MHz) (Pipelined)
Max. Access Time (ns) (Clock to Data, Pipelined)
Typical Operating Current I
CC
(mA)
Typical Standby Current for I
SB1
(mA)
(Both Ports TTL Level)
Typical Standby Current for I
SB3
(mA)
(Both Ports CMOS Level)
0.05
0.05
0.05
0.05
Pin Definitions
Left Port
A
0L
A
13L
ADS
L
Right Port
A
0R
A
13R
ADS
R
Description
Address Inputs (A
0
A
12
for 8K; A
0
A
13
for 16K devices).
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW during
normal read or write transactions. Asserting this signal LOW also loads the burst address counter
with data present on the I/O pins.
Chip Enable Input. To select either the left or right port, both CE
0
AND CE
1
must be asserted to
their active states (CE
0
V
IL
and CE
1
V
IH
).
Clock Signal. This input can be free running or strobed. Maximum clock input rate is f
MAX
.
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective
port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
Data Bus Input/Output (I/O
0
I/O
7
for x8 devices; I/O
0
I/O
8
for x9 devices).
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For
read operations, assert this pin HIGH.
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For
pipelined mode operation, assert this pin HIGH.
Ground Input.
No Connect.
Power Input.
CE
0L
,CE
1L
CE
0R
,CE
1R
CLK
L
CNTEN
L
CLK
R
CNTEN
R
CNTRST
L
CNTRST
R
I/O
0L
I/O
8L
OE
L
I/O
0R
I/O
8R
OE
R
R/W
L
R/W
R
FT/PIPE
L
FT/PIPE
R
GND
NC
V
CC
Operating Range
Range
Ambient
Temperature
0
°
C to +70
°
C
40
°
C to +85
°
C
V
CC
Commercial
Industrial
5V
±
10%
5V
±
10%
Shaded areas contain advance information.
相關PDF資料
PDF描述
CY7C09179A 32K x 9 Synchronous Dual-Port Static RAM(32K x 9 同步雙端口靜態(tài)RAM)
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CY7C09099A 128K x 8 Synchronous Dual-Port Static RAM(128K x 8 同步雙端口靜態(tài)RAM)
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相關代理商/技術參數(shù)
參數(shù)描述
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