參數(shù)資料
型號: CY7C09159
廠商: Cypress Semiconductor Corp.
英文描述: 8K x 9 Synchronous Dual-Port Static RAM(8K x 9 同步雙端口靜態(tài)RAM)
中文描述: 8K的× 9同步雙端口靜態(tài)存儲器(8K的× 9同步雙端口靜態(tài)RAM)的
文件頁數(shù): 15/18頁
文件大?。?/td> 324K
代理商: CY7C09159
CY7C09159
CY7C09169
PRELIMINARY
15
Notes:
24.
X
=
don
t care,
H
= V
IH
,
L
= V
.
25. ADS, CNTEN, CNTRST =
don
t care.
26. OE is an asynchronous input signal.
27. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle.
28. CE
and OE = V
; C
and R/W = V
29. Data shown for Flow-through mode; pipelined mode output will be delayed by one cycle.
30. Counter operation is independent of CE
0
and CE
1
.
Read/Write and Enable Operation
[24, 25, 26]
Inputs
CE
0
H
Outputs
I/O
0
I/O
8
High-Z
OE
CLK
CE
1
X
R/W
Operation
X
X
Deselected
[27]
X
X
L
X
High-Z
Deselected
[27]
X
L
H
L
D
IN
Write
L
L
H
H
D
OUT
Read
[27]
H
X
L
H
X
High-Z
Outputs Disabled
Address Counter Control Operation
[24, 28, 29, 30]
Address
X
Previous
Address
X
CLK
ADS
X
CNTEN
X
CNTRST
L
I/O
Mode
Reset
Operation
D
out(0)
Counter Reset to Address 0
A
n
X
L
X
H
D
out(n)
Load
Address Load into Counter
X
A
n
H
H
H
D
out(n)
Hold
External Address Blocked
Counter
Disabled
Counter Enabled
Internal Address
Generation
X
A
n
H
L
H
D
out(n+1)
Increment
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