參數(shù)資料
型號(hào): CY7C09099
廠商: Cypress Semiconductor Corp.
英文描述: 128K x 8 Synchronous Dual-Port Static RAM(128K x 8 同步雙端口靜態(tài)RAM)
中文描述: 128K的× 8同步雙端口靜態(tài)存儲(chǔ)器(128K的× 8同步雙端口靜態(tài)RAM)的
文件頁數(shù): 20/20頁
文件大?。?/td> 337K
代理商: CY7C09099
CY7C09079/89/99
CY7C09179/89/99
PRELIMINARY
Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C036 Dual-Port Design Consideration
Data Sheet Addendum
This design consideration applies to the Internal Power-On-
Reset (POR) circuit used on the CY7C036 and its derivatives
listed below.
Power supply ramp
The devices will function properly and
meet all data sheet specifications if the power supply ramp rate
is greater than 100 ns. If ramp is less than 100 ns, you may
see a non-destructive failure in which the device will not re-
spond to changes in address or clock, but the I/Os will respond
to the output enable.
Applications consideration
If the power supply ramps in less
than 100 ns, a small resistor (20
50
), a large capacitor, or an
RC network can be connected at the output of the power sup-
ply to ground. The addition of a resistor will help clean up the
power lines, while the capacitor will slow down the ramp rate
without the loss of any power. Contact your local Cypress FAE
for assistance as needed.
Troubleshooting
If a problem occurs with the part, power
down the device to ground and then power up again at slower
ramp rate (greater than 100 ns) in order to confirm that the
problem might be due to the POR circuit. If the dual-port func-
tions properly once the ramp rate is slowed to 100 ns or great-
er, then the POR circuit is at fault.
Applicable devices
All speed/package/temperature combi-
nations of the following:
CY7C09079
CY7C09179
Cypress design change
Cypress design team has identified
the root cause. A permanent circuit change and die revision
will be available beginning in October and will be identified by
the letter
A
in the part number.
相關(guān)PDF資料
PDF描述
CY7C09189 64K x 9 Synchronous Dual-Port Static RAM(64K x 9 同步雙端口靜態(tài)RAM)
CY7C09199 128K x 9 Synchronous Dual-Port Static RAM(128K x 9 同步雙端口靜態(tài)RAM)
CY7C09289A 64K x16 Synchronous Dual Port Static RAM(64K x 16 同步雙端口靜態(tài) RAM)
CY7C09269A 16K x16 Synchronous Dual Port Static RAM(16K x 16 同步雙端口靜態(tài) RAM)
CY7C09279A 32K x16 Synchronous Dual Port Static RAM(32K x 16 同步雙端口靜態(tài) RAM)
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