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參數(shù)資料
| 型號： | CY7C0851AV-167BBC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| 中文描述： | 64K X 36 DUAL-PORT SRAM, 4 ns, PBGA172 |
| 封裝： | 15 X 15 MM, 1.25 MM HEIGHT, 1 MM PITCH, FBGA-172 |
| 文件頁數(shù)： | 29/32頁 |
| 文件大?。?/td> | 971K |
| 代理商： | CY7C0851AV-167BBC |
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CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
Document #: 38-06070 Rev. *H
Page 6 of 32
Pin Definitions
Left Port
Right Port
Description
Address Inputs.
ADSL[3]
ADSR[3]
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW for
the part using the externally supplied address on the address pins and for loading this address
into the burst address counter.
CE0L[3]
CE0R[3]
Active LOW Chip Enable Input.
CE1L[3]
CE1R[3]
Active HIGH Chip Enable Input.
CLKL
CLKR
Clock Signal. Maximum clock input rate is fMAX.
CNTENL[3]
CNTENR[3]
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST are
asserted LOW.
CNTRSTL[3]
CNTRSTR[3]
Counter Reset Input. Asserting this signal LOW resets to zero the unmasked portion of the burst
address counter of its respective port. CNTRST is not disabled by asserting ADS or CNTEN.
CNT/MSKL[3]
CNT/MSKR[3]
Address Counter Mask Register Enable Input. Asserting this signal LOW enables access to
the mask register. When tied HIGH, the mask register is not accessible and the address counter
operations are enabled based on the status of the counter control signals.
DQ0L–DQ35L
DQ0R–DQ35R
Data Bus Input/Output.
OEL
OER
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data
pins during Read operations.
INTLINTR
Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The upper
two memory locations can be used for message passing. INTL is asserted LOW when the right
port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is
deasserted HIGH when it reads the contents of its mailbox.
CNTINTL[3]
CNTINTR[3]
Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of the counter
is incremented to all “1s.”
R/WL
R/WR
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual port
memory array.
B0L–B3L
B0R–B3R
Byte Select Inputs. Asserting these signals enables Read and Write operations to the corre-
sponding bytes of the memory array.
MRST
Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting
MRST LOW performs all of the reset functions as described in the text. A MRST operation is
required at power up.
TMS
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK.
TDI
JTAG Test Data Input. Data on the TDI input is shifted serially into selected registers.
TCK
JTAG Test Clock Input.
TDO
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally
three-stated except when captured data is shifted out of the JTAG TAP.
VSS
Ground Inputs.
VDD
Power Inputs.
Note
3. These pins are not available for CY7C0853AV device.
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C0852AV-133BBC | FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0851AV-133AXI | FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0851AV-133BBI | FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0851AV-167BBXC | FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0852AV-133AXC | FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C0851AV-167BBXC | 功能描述:靜態(tài)隨機存取存儲器 2MB (64Kx36) 3.3v 167MHz Sync 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C0851V-133AC | 制造商:Rochester Electronics LLC 功能描述:64K X 36 SYNC DPSRAM - Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C0851V-133AXC | 功能描述:IC SRAM 2MBIT 133MHZ 176LQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應商設備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C0851V-133AXCT | 功能描述:IC SRAM 2MBIT 133MHZ 176LQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應商設備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C0851V-133BBC | 制造商:Rochester Electronics LLC 功能描述:64K X 36 SYNC DPSRAM - Bulk 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 2.25M-Bit 64K x 36 4.4ns 172-Pin FBGA |
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