- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379052 > CY7C0832AV (Cypress Semiconductor Corp.) FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM) PDF資料下載
參數(shù)資料
| 型號： | CY7C0832AV |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM) |
| 中文描述： | FLEx18 3.3 64K/128K × 36和128K/256K × 18同步雙口RAM（FLEx18 3.3 64K/128K × 36和128K/256K × 18同步雙端口RAM）的 |
| 文件頁數(shù)： | 5/28頁 |
| 文件大?。?/td> | 775K |
| 代理商： | CY7C0832AV |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Document #: 38-06059 Rev. *Q
Page 5 of 28
Pin Definitions
Byte Select Operation
Left Port
A
0L
–A
18L[1]
ADS
L[7]
Right Port
A
0R
–A
18R[1]
ADS
R[7]
Description
Address Inputs
.
Address Strobe Input
. Used as an address qualifier. This signal should be asserted LOW
for the part using the externally supplied address on the address pins and for loading this
address into the burst address counter.
CE0
L[7]
CE1
L[6]
CLK
L
CNTEN
L[7]
CE0
R[7]
CE1
R[6]
CLK
R
CNTEN
R[7]
Active LOW Chip Enable Input
.
Active HIGH Chip Enable Input
.
Clock Signal
. Maximum clock input rate is f
MAX
.
Counter Enable Input
.
Asserting this signal LOW increments the burst address counter of
its respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST
are asserted LOW.
CNTRST
L[6]
CNTRST
R[6]
Counter Reset Input
. Asserting this signal LOW resets to zero the unmasked portion of
the burst address counter of its respective port. CNTRST is not disabled by asserting ADS
or CNTEN.
CNT/MSK
L[6]
CNT/MSK
R[6]
Address Counter Mask Register Enable Input
. Asserting this signal LOW enables access
to the mask register. When tied HIGH, the mask register is not accessible and the address
counter operations are enabled based on the status of the counter control signals.
DQ
0L
–DQ
17L[1]
OE
L
DQ
0R
–DQ
17R[1]
OE
R
Data Bus Input/Output
.
Output Enable Input
. This asynchronous signal must be asserted LOW to enable the DQ
data pins during Read operations.
INTL
INTR
Mailbox Interrupt Flag Output
.
The mailbox permits communications between ports. The
upper two memory locations can be used for message passing. INT
L
is asserted LOW when
the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a
port is deasserted HIGH when it reads the contents of its mailbox.
CNTINT
L[8]
CNTINT
R[8]
Counter Interrupt Output
. This pin is asserted LOW when the unmasked portion of the
counter is incremented to all “1s.”
R/W
L
R/W
R
Read/Write Enable Input
. Assert this pin LOW to write to, or HIGH to Read from the dual
port memory array.
B
0L
–B
1L
B
0R
–B
1R
Byte Select Inputs
. Asserting these signals enables Read and Write operations to the
corresponding bytes of the memory array.
MRST
Master Reset Input
. MRST is an asynchronous input signal and affects both ports.
Asserting MRST LOW performs all of the reset functions as described in the text. A MRST
operation is required at power-up.
TMS
JTAG Test Mode Select Input
. It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK.
TDI
JTAG Test Data Input
. Data on the TDI input will be shifted serially into selected registers.
TCK
JTAG Test Clock Input
.
TDO
JTAG Test Data Output
. TDO transitions occur on the falling edge of TCK. TDO is normally
three-stated except when captured data is shifted out of the JTAG TAP.
V
SS
V
DD
Ground Inputs
.
Power Inputs
.
Control Pin
Effect
B
0
B
1
DQ
0–8
Byte Control
DQ
9–17
Byte Control
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C0833AV | FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM) |
| CY7C0837AV | FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM) |
| CY7C0851V | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM(FLEx36TM 3.3V 32K/64K/128K/256K x 36同步雙端口RAM) |
| CY7C0852V | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0850V | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C0832AV-133AC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 4.5MBIT 256KX18 4.4NS 120TQFP - Trays |
| CY7C0832AV-133AI | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 4.5MBIT 256KX18 4.4NS 120TQFP - Trays |
| CY7C0832AV-133AXC | 功能描述:靜態(tài)隨機(jī)存取存儲器 Flex18 4M Sync Dual-Port RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C0832AV-133AXI | 功能描述:靜態(tài)隨機(jī)存取存儲器 4MB (256Kx18) 3.3v 133MHz Synch 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C0832AV-133BBC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 4M-Bit 256K x 18 4.4ns 144-Pin FBGA 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。