參數(shù)資料
型號: CY7C017AV-20JI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM
中文描述: 32K X 9 DUAL-PORT SRAM, 20 ns, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 13/20頁
文件大?。?/td> 301K
代理商: CY7C017AV-20JI
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Document #: 38-06051 Rev. *A
Page 13 of 20
Note:
42. If t
PS
is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
Switching Waveforms
(continued)
ADDRESS MATCH
t
PS
t
BLC
t
BHC
ADDRESS MATCH
t
PS
t
BLC
t
BHC
CE
R
ValidFirst:
ADDRESS
L,R
BUSY
R
CE
L
CE
R
BUSY
L
CE
R
CE
L
ADDRESS
L,R
Busy Timing Diagram No. 1 (CE Arbitration)
[42]
CE
L
Valid First:
ADDRESS MATCH
t
PS
ADDRESS
L
BUSY
R
ADDRESS MISMATCH
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
L
BUSY
L
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
Right AddressValid First:
Busy Timing Diagram No. 2 (Address Arbitration)
[42]
Left Address Valid First
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