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參數(shù)資料
| 型號： | CY7C016AV-20JC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM |
| 中文描述： | 16K X 9 DUAL-PORT SRAM, 20 ns, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 301K |
| 代理商： | CY7C016AV-20JC |
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Document #: 38-06051 Rev. *A
Page 2 of 20
Functional Description
The CY7C138AV/144AV/006AV/007AV and CY7C139AV/
145AV/ 016AV/017AV are low-power CMOS 4K, 8K, 16K, and
32K x8/9 dual-port static RAMs. Various arbitration schemes
are included on the devices to handle situations when multiple
processors access the same piece of data. Two ports are pro-
vided, permitting independent, asynchronous access for reads
and writes to any location in memory. The devices can be uti-
lized as standalone 8/9-bit dual-port static RAMs or multiple
devices can be combined in order to function as a 16/18-bit or
wider master/slave dual-port static RAM. An M/S pin is provid-
ed for implementing 16/18-bit or wider memory applications
without the need for separate master and slave devices or
additional discrete logic. Application areas include interpro-
cessor/multiprocessor designs, communications status buffer-
ing, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY sig-
nals that the port is trying to access the same location currently
being accessed by the other port. The Interrupt flag (INT) per-
mits communication between ports or systems by means of a
mail box. The semaphores are used to pass a flag, or token,
from one port to the other to indicate that a shared resource is
in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared re-
source is in use. An automatic power-down feature is con-
trolled independently on each port by a Chip Select (CE) pin.
Pin Configurations
Notes:
4.
5.
I/O
8L
on the CY7C139AV.
I/O
8R
on the CY7C139AV.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
67
Top View
68-Pin PLCC
60
59
58
57
56
55
54
53
52
51
50
49
48
3132 33 34 35 36 37 38 39 40 41 42 43
5 4 3 2 1 68
66 65 64 63 62 61
A
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
A
2728 29 30
9 8 7 6
47
46
45
44
6
7
A8
A9
A
A
1
1
V
N
N
CL
SL
RL
O
N
I
I
1
0
A
A
6
7
A8
A9
A1
N
N
CR
SR
RR
O
R
I7
G
A1
A5
A
5L
N
CY7C138AV (4K x 8)
CY7C139AV (4K x 9)
[
[
N
N
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C026AV-20AC | 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM |
| CY7C1362B-166BZI | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| CY7C1362B-166BZC | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| CY7C1362B-225BZC | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C016AV-25JC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM |
| CY7C017A | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:32K/16K x8, 32K/16K x9 Dual-Port Static RAM |
| CY7C017A-12JC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:32K/16K x8, 32K/16K x9 Dual-Port Static RAM |
| CY7C017A-15JC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:32K/16K x8, 32K/16K x9 Dual-Port Static RAM |
| CY7C017A-15JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
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