參數(shù)資料
型號(hào): CY7C007
廠商: Cypress Semiconductor Corp.
英文描述: 32K x 8 Dual-Port Static RAM(32K x 8位 雙端口靜態(tài)RAM)
中文描述: 32K的× 8雙端口靜態(tài)存儲(chǔ)器(32K的× 8位雙端口靜態(tài)RAM)的
文件頁(yè)數(shù): 1/17頁(yè)
文件大小: 212K
代理商: CY7C007
PRELIMINARY
32K x 8/9
Dual-Port Static RAM
CY7C007
CY7C017
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
November 30, 1999
1
Features
True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
32K x 8 organization (CY7C007)
32K x 9 organization (CY7C017)
0.35-micron CMOS for optimum speed/power
High-speed access: 12
[1]
/15/20 ns
Low operating power
—Active: I
CC
= 180 mA (typical)
—Standby: I
SB3
= 0.05 mA (typical)
Fully asynchronous operation
Automatic power-down
Expandable data bus to 16/18 bits or more using Mas-
ter/Slave chip select when using more than one device
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flags for port-to-port communication
Pin select for Master or Slave
Commercial and Industrial temperature ranges
Available in 68-pin PLCC
Pin-compatible and functionally equivalent to IDT7007
Notes:
1.
2.
3.
See page 5 for Load Conditions.
I/O
–I/O
for x8 devices; I/O
–I/O
for x9 devices.
BUSY is an output in master mode and an input in slave mode.
I/O
Control
Address
Decode
A
0L
–A
14L
CE
L
OE
L
R/W
L
SEM
L
BUSY
L
INT
L
I/O
Control
Interrupt
Semaphore
Arbitration
M/S
Logic Block Diagram
A
0L
–A
14L
True Dual-Ported
RAM Array
A
0R
–A
14R
CE
R
OE
R
R/W
R
SEM
R
BUSY
R
INT
R
Address
Decode
A
0R
–A
14R
[2]
[2]
[3]
[3]
R/W
L
OE
L
I/O
0L
–I/O
7/8L
CE
L
R/W
R
OE
R
I/O
0R
–I/O
7/8R
CE
R
15
8/9
15
8/9
15
15
For the most recent information, visit the Cypress web site at www.cypress.com
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