參數(shù)資料
型號(hào): CY7C019V
廠商: Cypress Semiconductor Corp.
英文描述: 3.3V 128Kx9 Dual-Port Static RAM(3.3V 128Kx 9 位雙端口靜態(tài)RAM)
中文描述: 3.3 128Kx9雙端口靜態(tài)RAM(3.3 128Kx 9位雙端口靜態(tài)RAM)的
文件頁數(shù): 1/18頁
文件大小: 493K
代理商: CY7C019V
3.3V 64K/128K x 8/9
Dual-Port Static RAM
CY7C008V/009V
CY7C018V/019V
Cypress Semiconductor Corporation
Document #: 38-06044 Rev. *C
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised September 6, 2005
Features
True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
64K x 8 organization (CY7C008)
128K x 8 organization (CY7C009)
64K x 9 organization (CY7C018)
128K x 9 organization (CY7C019)
0.35-micron CMOS for optimum speed/power
High-speed access: 15/20/25 ns
Low operating power
— Active: I
CC
= 115 mA (typical)
— Standby: I
SB3
= 10
μ
A (typical)
Fully asynchronous operation
Automatic power-down
Expandable data bus to 16/18 bits or more using
Master/Slave chip select when using more than one
device
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flag for port-to-port communication
Dual Chip Enables
Pin select for Master or Slave
Commercial and Industrial Temperature Ranges
Available in 100-pin TQFP
Pb-Free packages available
Notes:
1. I/O
0
–I/O
for x8 devices; I/O
0
–I/O
for x9 devices.
2. A
–A
for 64K devices; A
–A
for 128K.
3. BUSY is an output in master mode and an input in slave mode.
I/O
Control
Address
Decode
A
0L
–A
15/16L
CE
L
OE
L
R/W
L
SEM
L
BUSY
L
INT
L
I/O
Control
Interrupt
Semaphore
Arbitration
M/S
Logic Block Diagram
A
0L
–A
15/16L
True Dual-Ported
RAM Array
A
0R
–A
15/16R
CE
R
OE
R
R/W
R
SEM
R
BUSY
R
INT
R
Address
Decode
A
0R
–A
15/16R
[1]
[1]
[2]
[3]
[3]
[2]
R/W
L
CE
0L
CE
1L
OE
L
I/O
0L
–I/O
7/8L
CE
L
R/W
R
CE
0R
CE
1R
OE
R
I/O
0R
–I/O
7/8R
CE
R
16/17
8/9
16/17
8/9
16/17
16/17
CY7C008V CY7C018V CY7C009V CY7C019V 3.3V 64K/128K x 8/9
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CY7C016A-20AC 32K/16K x8, 32K/16K x9 Dual-Port Static RAM
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