參數(shù)資料
型號: CY7C006
廠商: Cypress Semiconductor Corp.
英文描述: 16K x 8 Dual-Port Static RAM with Sem, Int, Busy(帶Sem、 Int、 Busy雙端口靜態(tài)RAM)
中文描述: 16K的× 8雙端口靜態(tài)存儲器與掃描電鏡,廉政,忙(帶掃描電鏡,廉政,忙雙端口靜態(tài)RAM)的
文件頁數(shù): 1/16頁
文件大?。?/td> 319K
代理商: CY7C006
16K x 8/9 Dual-Port Static RAM
with Sem, Int, Busy
schemes are included on the CY7C006/016 to handle situa-
tions when multiple processors access the same piece of data.
Two ports are provided, permitting independent, asynchro-
nous access for reads and writes to any location in memory.
The CY7C006/016 can be utilized as a standalone
128-/144-Kbit dual-port static RAM or multiple devices can be
combined in order to function as a 16-/18-bit or wider mas-
ter/slave dual-port static RAM. An M/S pin is provided for im-
plementing 16-/18-bit or wider memory applications without
the need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor/multi-
processor designs, communications status buffering, and du-
al-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags, BUSY and INT, are provided on each port. BUSY signals
that the port is trying to access the same location currently
being accessed by the other port. The Interrupt flag (INT) per-
mits communication between ports or systems by means of a
mail box. The semaphores are used to pass a flag, or token,
from one port to the other to indicate that a shared resource is
in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared re-
source is in use. An automatic power-down feature is con-
trolled independently on each port by a Chip Enable (CE) pin
or SEM pin.
The CY7C006 and CY7C016 are available in 68-pin PLCC
(CY7C006), 64-pin (CY7C006) TQFP and 80-pin (CY7C016) TQFP
CY7C006
CY7C016
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
December 22, 1999
Features
True dual-ported memory cells which allow
simultaneous reads of the same memory location
16K x 8 organization (CY7C006)
16K x 9 organization (CY7C016)
0.65-micron CMOS for optimum speed/power
High-speed access: 15 ns
Low operating power: I
CC
= 140 mA (typ.)
Fully asynchronous operation
Automatic power-down
TTL compatible
Expandable data bus to 16/18 bits or more using
Master/Slave chip select when using more than one
device
Busy arbitration scheme provided
Semaphores included to permit software handshaking
between ports
INT flag for port-to-port communication
Available in 68-pin PLCC (7C006), 64-pin (7C006) and
80-pin (7C016) TQFP
Pin compatible and functional equivalent to
IDT7006/IDT7016
Functional Description
The CY7C006 and CY7C016 are high-speed CMOS 16K x 8
and 16K x 9 dual-port static RAMs. Various arbitration
Notes:
1.
2.
BUSY is an output in master mode and an input in slave mode.
Interrupt: push-pull output and requires no pull-up resistor.
C006-1
R/W
L
CE
L
OE
L
A
13L
A
0L
A
0R
A
13R
R/W
R
CE
R
OE
R
CE
R
OE
R
CE
L
OE
L
R/W
L
R/W
R
I/O
7L
I/O
0L
I/O
7R
I/O
0R
INTERRUPT
SEMAPHORE
ARBITRATION
CONTROL
I/O
CONTROL
I/O
MEMORY
ARRAY
ADDRESS
ADDRESS
DECODER
SEM
L
INT
L
SEM
R
INT
R
BUSY
L
BUSY
R
M/S
(7C016)I/O
8L
I/O
8R
(7C016)
[1,2]
[1,2]
[2]
[2]
Logic Block Diagram
with Sem, Int, Busy
相關(guān)PDF資料
PDF描述
CY7C016 16K x 9 Dual-Port Static RAM with Sem, Int, Busy( 帶Sem, Int, Busyy輸入端的16K x 9位雙端口靜態(tài)RAM)
CY7C007 32K x 8 Dual-Port Static RAM(32K x 8位 雙端口靜態(tài)RAM)
CY7C017 32K x 9 Dual-Port Static RAM(32K x 9位 雙端口靜態(tài)RAM)
CY7C009V 3.3V 128Kx8 Dual-Port Static RAM(3.3V 128Kx 8 位雙端口靜態(tài)RAM)
CY7C018V 3.3V 64Kx9 Dual-Port Static RAM(3.3V 64Kx 9 位雙端口靜態(tài)RAM)
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