參數(shù)資料
型號： CY7B9950AIT
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 時鐘及定時
英文描述： Precision, High-Side Current-Sense Amplifiers
中文描述： 7B SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝： 7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32
文件頁數(shù)： 2/9頁
文件大小： 168K
代理商： CY7B9950AIT
RoboClock
CY7B9950
Document #: 38-07338 Rev. *B
Page 2 of 9
Device Configuration
The outputs of the CY7B9950 can be configured to run at
frequencies ranging from 6 to 200 MHz. Banks 3 and 4 output
dividers are controlled by 3F[1:0] and 4F[1:0] as indicated in
Table 1
and
Table 2
,
respectively.
The three-level FS control pin setting determines the nominal
operating frequency range of the divide-by-one outputs of the
device. The CY7B9950 PLL operating frequency range that
corresponds to each FS level is given in
Table 3
.
Selectable output skew is in discrete increments of time unit
(t
U
).The value of t
U
is determined by the FS setting and the
maximum nominal frequency. The equation to be used to
determine the t
U
value is as follows: t
U
= 1 / (f
NOM
x MF)
where MF is a multiplication factor, which is determined by the
FS setting as indicated in
Table 4
.
Notes:
1.
2.
“
PD
”
indicates an internal pull-down and
“
PU
”
indicates an internal pull-up.
“
3
”
indicates a three-level input buffer
A bypass capacitor (0.1
μ
F) should be placed as close as possible to each positive power pin (< 0.2
”
). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections
remain in effect unless nF[1:0] = LL.
These states are used to program the phase of the respective banks (see
Table 5
)
.
3.
4.
Pin Description
Pin
Name
REF
FB
TEST
I/O
[1]
I
I
I
Type
Description
29
13
27
LVTTL/LVCMOS
LVTTL
Three-level
Reference Clock Input
.
Feedback Input
.
When MID or HIGH, Disables Phase-locked Loop (PLL)
(except for condi-
tions of
note
3
). REF goes to outputs of Bank 1 and Bank 2. REF goes to
outputs of Bank 3 and Bank 4 through output dividers K and M. Set LOW for
normal operation.
Synchronous Output Enable
. When HIGH, it stops clock outputs (except 2Q0
and 2Q1) in a LOW state (for PE = H or M)
–
2Q0 and 2Q1 may be used as
the feedback signal to maintain phase lock. When TEST is held at MID level
and sOE# is HIGH, the nF[1:0] pins act as output disable controls for individual
banks when nF[1:0] = LL. Set sOE# LOW for normal operation.
Selects Positive or Negative Edge Control and High or Low output drive
strength
. When LOW/HIGH the outputs are synchronized with the
negative/positive edge of the reference clock, respectively. When at MID level,
the output drive strength is increased and the outputs synchronize with the
positive edge of the reference clock (see
Table 6
).
Select frequency and phase of the outputs
(see
Tables 1, 2, 3, 4, and 5).
22
sOE#
I, PD
Two-level
4
PE/HD
I, PU
Three-level
24, 23, 26,
25, 1, 32, 3,
2
31
19, 20, 15,
16, 10, 11,
6, 7
21
nF[1:0]
I
Three-level
FS
I
Three-level
LVTTL
Selects VCO operating frequency range
(see
Table 4
).
Four banks of two outputs
(see
Tables 1, 2, and 3).
nQ[1:0]
O
V
DDQ1[2]
PWR
Power
Power supply for Bank 1 and Bank 2 output buffers
(see
Table 7
for supply
level constraints).
Power supply for Bank 3 output buffers
(see
Table 7
for supply level
constraints).
Power supply for Bank 4 output buffers
(see
Table 7
for supply level
constraints).
Power supply for internal circuitry
(see
Table 7
for supply level constraints).
12
V
DDQ3[2]
PWR
Power
5
V
DDQ4[2]
PWR
Power
14,30
8,9,17,18,
28
V
DD[2]
V
SS
PWR
PWR
Power
Power
Ground
.
Table 1. Output Divider Settings
—
Bank 3
3F[1:0]
LL
HH
Other
[4]
K
—
Bank3 Output Divider
2
4
1
Table 2. Output Divider Settings
—
Bank 4
4F[1:0]
LL
Other
[4]
M
—
Bank4 Output Divider
2
1
Table 3. Frequency Range Select
FS
L
M
H
PLL Frequency Range
24 to 50 MHz
48 to 100 MHz
96 to 200 MHz
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