參數(shù)資料
型號: CY7B9950AI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 時鐘及定時
英文描述: 2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer
中文描述: 7B SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: 7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32
文件頁數(shù): 6/9頁
文件大?。?/td> 168K
代理商: CY7B9950AI
RoboClock
CY7B9950
Document #: 38-07338 Rev. *B
Page 6 of 9
AC Input Specifications
Notes:
10. Test load = 20 pF, terminated to V
/2. All outputs are equally loaded.
11.
t
PD
is measured at 1.5V for V
= 3.3V and at 1.25V for V
= 2.5V with REF rise/fall times of 0.5 ns between 0.8V
2.0V.
12. t
is the time that is required before outputs synchronize to REF. This specification is valid with stable power supplies which are within normal operating limits.
13. Lock detector circuit may be unreliable for input frequencies lower than 4 MHz, or for input signals which contain significant jitter.
Parameter
T
R
,T
F
T
PWC
T
DCIN
F
REF
Description
Condition
Min.
2
10
6
12
24
Max.
10
90
50
100
200
Unit
ns/V
ns
%
Input Rise/Fall Time
Input Clock Pulse
Input Duty Cycle
Reference Input Frequency
0.8V
2.0V
HIGH or LOW
FS = LOW
FS = MID
FS = HIGH
MHz
Switching Characteristics
Parameter
F
OR
VCO
LR
VCO
LBW
t
SKEWPR
Description
Condition
Min.
6
200
0.25
Max.
200
400
3.5
Unit
MHz
MHz
MHz
Output Frequency Range
VCO Lock Range
VCO Loop Bandwidth
Matched-Pair Skew
[10]
Skew between the earliest and the latest output transitions within
the same bank.
Skew between the earliest and the latest output transitions
among all outputs at 0t
U
.
Skew between the earliest and the latest output transitions
among all outputs for which the same phase delay has been
selected.
Skew between the nominal output rising edge to the inverted
output falling edge
Skew between non-inverted outputs running at different
frequencies
Skew between nominal to inverted outputs running at different
frequencies
Skew between nominal outputs at different power supply levels
Skew between the outputs of any two devices under identical
settings and conditions (V
DDQ
,V
DD
,temp, air flow, frequency, etc.)
100
ps
t
SKEW0
Output-Output Skew
[10]
200
ps
t
SKEW1
200
ps
t
SKEW2
500
ps
t
SKEW3
Output-Output Skew
[10]
500
ps
t
SKEW4
500
ps
t
SKEW5
t
PART
650
ps
Part-Part Skew
750
ps
t
PD0
Ref-FB Propagation
Delay
[11]
Output Duty Cycle
250
+250
ps
t
ODCV
Fout < 100 MHz, measured at V
DD
/2
Fout > 100 MHz, measured at V
DD
/2
48
45
52
55
%
t
PWH
Output High Time
Deviation from 50%
Output Low Time
Deviation from 50%
Output Rise/Fall Time
PLL lock time
[12,13]
Cycle-Cycle Jitter
Measured at 2.0V for V
DD
= 3.3V and at 1.7V for V
DD
= 2.5V.
1.5
ns
t
PWL
Measured at 0.8V for V
DD
= 3.3V and at 0.7V for V
DD
= 2.5V.
2.0
ns
t
R
/t
F
t
LOCK
t
CCJ
Measured at 0.8V
2.0V for V
DD
= 3.3V and 0.7V
1.7V for V
DD
= 2.5V
0.15
1.5
0.5
100
150
ns
ms
ps
ps
Divide by 1 output frequency, FS = L, FB = divide by 1,2,4
Divide by 1 output frequency, FS = M/H, FB = divide by 1,2,4
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