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參數(shù)資料
| 型號： | CY7B9920-7SI[20] |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Low Skew Clock Buffer |
| 中文描述： | 低偏移時鐘緩沖器 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大小： | 281K |
| 代理商： | CY7B9920-7SI[20] |
CY7B9910
CY7B9920
Document Number: 38-07135 Rev. *B
Page 5 of 11
AC Test Loads and Waveforms
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
C
IN
Input Capacitance
Test Conditions
Max
10
Unit
pF
T
A
= 25
°
C, f = 1 MHz, V
CC
= 5.0V
7B9910–3
7B9910–4
TTL AC Test Load (CY7B9910)
TTL Input Test Waveform (Cy7B9910)
5V
R1
R2
C
L
R1
R2
C
L
7B9910–5
CMOS AC Test Load (CY7B9920)
Switching Characteristics
3.0V
2.0V
V
th
=1.5V
0.8V
0.0V
≤
1ns
≤
1ns
2.0V
V
=1.5V
0.8V
80%
V
th
= V
CC
/2
20%
0.0V
≤
3ns
≤
3ns
80%
V
th
= V
CC
/2
20%
7B9910–6
CMOS Input Test Waveform (CY7B9920)
V
CC
R1=130
R2=91
C
= 50 pF (C
= 30pF for –5 and –2 devices)
(Includes fixture and probe capacitance)
R1=100
R2=100
C
L
= 50 pF (C
L
=30 pF for –5 and –2devices)
(Includes fixture and probe capacitance)
V
CC
Over the Operating Range
[11]
CY7B9910–2
[8]
Min
Typ
15
25
40
5.0
5.0
0.1
CY7B9920–2
[8]
Min
Typ
15
25
40
5.0
5.0
0.1
Parameter
f
NOM
Description
Max
30
50
80
Max
30
50
80
[12]
Unit
MHz
Operating Clock
Frequency in MHz
FS = LOW
[1, 2]
FS = MID
[1, 2]
FS = HIGH
[1, 2, 3]
t
RPWH
t
RPWL
t
SKEW
t
DEV
t
PD
t
ODCV
t
ORISE
t
OFALL
t
LOCK
t
JR
REF Pulse Width HIGH
REF Pulse Width LOW
Zero Output Skew (All Outputs)
[13, 14]
Device-to-Device Skew
[14, 15]
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation
[16]
Output Rise Time
[17, 18]
Output Fall Time
[17, 18]
PLL Lock Time
[19]
Cycle-to-Cycle Output Jitter Peak to Peak
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
0.25
0.75
+0.25
+0.65
1.2
1.2
0.5
200
25
0.25
0.75
+0.25
+0.65
2.5
2.5
0.5
200
25
–0.25
–0.65
0.15
0.15
0.0
0.0
1.0
1.0
–0.25
–0.65
0.5
0.5
0.0
0.0
2.0
2.0
RMS
[+] Feedback
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