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參數(shù)資料
| 型號(hào)： | CY7B9910-5SXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Low Skew Clock Buffer |
| 中文描述： | 7B SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 0.300 INCH, LEAD FREE, MO-119, SOIC-24 |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大?。?/td> | 281K |
| 代理商： | CY7B9910-5SXC |
CY7B9910
CY7B9920
Low Skew Clock Buffer
Cypress Semiconductor Corporation
Document Number: 38-07135 Rev. *B
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised August 07, 2007
Features
■
All outputs skew <100 ps typical (250 max.)
■
15 to 80 MHz output operation
■
Zero input to output delay
■
50% duty cycle outputs
■
Outputs drive 50
Ω
terminated lines
■
Low operating current
■
24-pin SOIC package
■
Jitter:<200 ps peak to peak, <25 ps RMS
Functional Description
The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer
low skew system clock distribution. These multiple output clock
drivers optimize the timing of high performance computer
systems. Each of the eight individual drivers can drive terminated
transmission lines with impedances as low as 50
Ω
. They deliver
minimal and specified output skews and full swing logic levels
(CY7B9910 TTL or CY7B9920 CMOS).
The completely integrated PLL enables “zero delay” capability.
External divide capability, combined with the internal PLL, allows
distribution of a low frequency clock that is multiplied by virtually
any factor at the clock destination. This facility minimizes clock
distribution difficulty while allowing maximum system clock
speed and flexibility.
Block Diagram Description
Phase Frequency Detector and Filter
The Phase Frequency Detector and Filter blocks accept inputs
from the reference frequency (REF) input and the feedback (FB)
input and generate correction information to control the
frequency of the Voltage Controlled Oscillator (VCO). These
blocks, along with the VCO, form a Phase Locked Loop (PLL)
that tracks the incoming REF signal.
VCO
The VCO accepts analog control inputs from the PLL filter block
and generates a frequency. The operational range of the VCO is
determined by the FS control pin.
TEST
FB
REF
VOLTAGE
CONTROLLED
OSCILLATOR
FS
Q0
FILTER
PHASE
FREQ
DET
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Logic Block Diagram
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7B9910-5SXCT | Low Skew Clock Buffer |
| CY7B9910-5SXI | Low Skew Clock Buffer |
| CY7B9910-5SXIT | Low Skew Clock Buffer |
| CY7B9910-2SXCT | Low Skew Clock Buffer |
| CY7B9910-5SCT | Low Skew Clock Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7B9910-5SXCT | 功能描述:鎖相環(huán) - PLL 5V 80MHz 8 TTL COM Not Programable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY7B9910-5SXI | 功能描述:鎖相環(huán) - PLL 5V 80MHz 8 TTL Outpt not programable Skew RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY7B9910-5SXIT | 功能描述:鎖相環(huán) - PLL 5V 80MHz 8 TTL Outpt not programable Skew RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY7B99107SC | 制造商:CYP 功能描述:7B9910 D/C:95 S8I1D |
| CY7B9910-7SC | 功能描述:IC CLK BUFF SKEW 8OUT 24SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:133.3MHz 除法器/乘法器:是/無(wú) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
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