參數(shù)資料
型號： CY7B9910-5SIT
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 時鐘及定時
英文描述： Low Skew Clock Buffer
中文描述： 7B SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
封裝： 0.300 INCH, MO-119, SOIC-24
文件頁數(shù)： 4/11頁
文件大?。?/td> 281K
代理商： CY7B9910-5SIT
CY7B9910
CY7B9920
Document Number: 38-07135 Rev. *B
Page 4 of 11
Electrical Characteristics
Over the Operating Range
CY7B9910
Min
2.4
CY7B9920
Min
Parameter
V
OH
Description
Test Conditions
V
CC
= Min, I
OH
= –16 mA
V
CC
= Min, I
OH
=–40 mA
V
CC
= Min, I
OL
= 46 mA
V
CC
= Min, I
OL
= 46 mA
Max
Max
Unit
V
Output HIGH Voltage
V
CC
–0.75
V
OL
Output LOW Voltage
0.45
V
0.45
V
CC
V
IH
Input HIGH Voltage
(REF and FB inputs only)
Input LOW Voltage
(REF and FB inputs only)
Three Level Input HIGH
Voltage (Test, FS)
[4]
Three Level Input MID
Voltage (Test, FS)
[4]
Three Level Input LOW
Voltage (Test, FS)
[4]
Input HIGH Leakage Current
(REF and FB inputs only)
Input LOW Leakage Current
(REF and FB inputs only)
Input HIGH Current
(Test, FS)
Input MID Current
(Test, FS)
Input LOW Current
(Test, FS)
Output Short Circuit
Current
[5]
Operating Current Used by
Internal Circuitry
2.0
V
CC
V
CC
–
1.35
–0.5
V
V
IL
–0.5
0.8
1.35
V
V
IHH
Min
≤
V
CC
≤
Max
V
CC
– 1V
V
CC
V
CC
– 1V
V
CC
V
V
IMM
Min
≤
V
CC
≤
Max
V
CC
/2 –
500 mV
0.0
V
CC
/2 +
500 mV
1.0
V
CC
/2 –
500 mV
0.0
V
CC
/2 +
500 mV
1.0
V
V
ILL
Min
≤
V
CC
≤
Max
V
I
IH
V
CC
= Max, V
IN
= Max
10
10
μ
A
I
IL
V
CC
= Max, V
IN
= 0.4V
–500
–500
μ
A
I
IHH
V
IN
= V
CC
200
200
μ
A
I
IMM
V
IN
= V
CC
/2
–50
50
–50
50
μ
A
I
ILL
V
IN
= GND
–200
–200
μ
A
I
OS
V
CC
= Max, V
OUT
= GND (25
°
C only)
V
CCN
= V
CCQ
= Max All
Input
Selects Open
V
CCN
= V
CCQ
= Max
I
OUT
= 0 mA
Input Selects Open, f
MAX
V
CCN
= V
CCQ
= Max
I
OUT
= 0 mA
Input Selects Open, f
MAX
–250
N/A
mA
I
CCQ
Com’l
Mil/Ind
85
90
85
90
mA
I
CCN
Output Buffer Current per
Output Pair
[6]
14
19
mA
PD
Power Dissipation per
Output Pair
[7]
78
104
[5]
mW
Notes
4. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time
before all data sheet limits are achieved.
5. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B9920 outputs are not short circuit
protected.
6. Total output current per output pair is approximated by the following expression that includes device current plus load current:
CY7B9910:
ICCN = [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1
CY7B9920:
ICCN = [(3.5+.17F) + [((1160 – 2.8F)/Z) + (.0025FC)]N] x 1.1
Where
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC = F < C.
7. Total power dissipation per output pair is approximated by the following expression that includes device power dissipation plus power dissipation due to the load circuit:
CY7B9910:
PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1
CY7B9920:
PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] x 1.1.See
note 3
for variable definition.
[+] Feedback
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