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參數(shù)資料
| 型號： | CY7B9910-2SXCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Low Skew Clock Buffer |
| 中文描述： | 7B SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 0.300 INCH, LEAD FREE, MO-119, SOIC-24 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 281K |
| 代理商： | CY7B9910-2SXCT |
CY7B9910
CY7B9920
Document Number: 38-07135 Rev. *B
Page 2 of 11
Pin Configuration
Test Mode
The TEST input is a three level input. In normal system operation, this pin is connected to ground, allowing the CY7B9910 and
CY7B9920 to operate as described in
Block Diagram Description
. For testing purposes, any of the three level inputs can have a
removable jumper to ground or be tied LOW through a 100W resistor. This enables an external tester to change the state of these pins.
If the TEST input is forced to its MID or HIGH state, the device operates with its internal phase locked loop disconnected and input
levels supplied to REF directly control all outputs. Relative output-to-output functions are the same as in normal mode.
Pin Definitions
Signal Name
REF
IO
I
Description
Reference frequency input.This input supplies the frequency and timing against which all functional
variations are measured.
PLL feedback input (typically connected to one of the eight outputs).
Three level frequency range select.
Three level select. See
TEST MODE
.
Clock outputs.
Power supply for output drivers.
Power supply for internal circuitry.
Ground.
FB
FS
[1,2,3]
TEST
Q[0..7]
V
CCN
V
CCQ
GND
I
I
I
O
PWR
PWR
PWR
Q4
V
CCN
FB
Q2
Q3
REF
V
CCQ
FS
NC
V
CCQ
V
CCN
Q0
Q1
GND
V
CCN
GND
TEST
NC
GND
V
CCN
Q7
Q6
GND
Q5
SOIC
Top View
1
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
24
23
22
21
13
14
7B9910
7B9920
Notes
1. For all three state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
circuitry holds an unconnected input to VCC/2.
2. The level to be set on FS is determined by the “normal” operating frequency (fNOM) of the VCO (see
Logic Block Diagram
). The frequency appearing at the REF
and FB inputs are fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs are fNOM/X when the device is configured for a
frequency multiplication by using external division in the feedback path of value X.
3. When the FS pin is selected HIGH, the REF input must not transition upon power up until VCC reached 4.3V.
[+] Feedback
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| CY7B9910-5SIT | Low Skew Clock Buffer |
| CY7B9950ACT | 2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7B9910-5SC | 功能描述:IC CLK BUFF SKEW 8OUT 24SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| CY7B9910-5SCT | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Buffer Single 15MHz to 80MHz 24-Pin SOIC T/R |
| CY7B9910-5SI | 功能描述:鎖相環(huán) - PLL 5V 80MHz 8 TTL IND Not Programable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY7B9910-5SIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Low Skew Clock Buffer |
| CY7B9910-5SXC | 功能描述:鎖相環(huán) - PLL 5V 80MHz 8 TTL COM Not Programable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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