參數(shù)資料
型號(hào): CY74FCT646TLCC
廠商: Texas Instruments, Inc.
英文描述: 8-Bit Registered Transceiver
中文描述: 8位注冊(cè)收發(fā)器
文件頁(yè)數(shù): 5/8頁(yè)
文件大?。?/td> 76K
代理商: CY74FCT646TLCC
CY54/74FCT646T
5
Switching Characteristics
Over the Operating Range
[14]
Parameter
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PLH
t
PHL
t
PLH
t
PHL
t
S
Description
FCT646T
FCT646AT
Commercial
Min.
1.5
Unit
ns
Fig.
No.
[15]
1, 3
Military
Min.
2.0
Commercial
Min.
1.5
Max.
11.0
Max.
9.0
Max.
6.3
Propagation Delay Bus to Bus
Output Enable Time
Enable to Bus and DIR to A
n
or B
n
Output Disable Time
G to Bus and DIR to Bus
Propagation Delay
Clock to Bus
Propagation Delay
SBA or SAB to A or B
Set-Up Time HIGH or LOW,
Bus to Clock
Hold Time HIGH or LOW,
Bus to Clock
Pulse Width, HIGH or LOW
[8]
2.0
15.0
1.5
14.0
1.5
9.8
ns
1, 7, 8
2.0
11.0
1.5
9.0
1.5
6.3
ns
1, 7, 8
2.0
10.0
1.5
9.0
1.5
6.3
ns
1, 5
2.0
12.0
1.5
11.0
1.5
7.7
ns
1, 5
4.5
4.0
2.0
ns
4
t
H
2.0
2.0
1.5
ns
4
t
W
6.0
6.0
5.0
ns
5
Parameter
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PLH
t
PHL
t
PLH
t
PHL
t
S
t
H
t
W
Notes:
14. Minimum limits are specified but not tested on Propagation Delays.
15. See “Parameter Measurement Information” in the General Information Section.
Description
FCT646CT
Unit
ns
Fig.
No.
[15]
1, 3
Military
Min.
1.5
Commercial
Min.
1.5
Max.
6.0
Max.
5.4
Propagation Delay Bus to Bus
Output Enable Time Enable to Bus and DIR to A
n
or B
n
1.5
8.9
1.5
7.8
ns
1, 7, 8
Output Disable Time G to Bus and DIR toBus
1.5
7.7
1.5
6.3
ns
1, 7, 8
Propagation Delay Clock to Bus
1.5
6.3
1.5
5.7
ns
1, 5
Propagation Delay SBA or SAB to A or B
1.5
7.0
1.5
6.2
ns
1, 5
Set-Up Time, HIGH or LOW, Bus to Clock
Hold Time, HIGH or LOW, Bus to Clock
Pulse Width,
[8]
HIGH or LOW
2.0
1.5
5.0
2.0
1.5
5.0
ns
ns
ns
4
4
5
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