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參數(shù)資料
| 型號(hào)： | CY54FCT841TQSOP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 10-Bit Latch |
| 中文描述： | 10位鎖存器 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 84K |
| 代理商： | CY54FCT841TQSOP |
10-Bit Latch
CY54/74FCT841T
SCCS035 - September 1994 - Revised March 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright
2000, Texas Instruments Incorporated
Features
Function,pinout,anddrivecompatiblewithFCT,F,and
AM29841 logic
FCT-C speed at 5.5 ns max. (Com’l)
FCT-B speed at 6.5 ns max. (Com’l)
Reduced V
(typically = 3.3V) versions of equivalent
FCT functions
Edge-rate control circuitry for significantly improved
noise characteristics
Power-off disable feature
Matched rise and fall times
ESD > 2000V
Fully compatible with TTL input and output logic levels
Sink current
64 mA (Com’l),
32 mA (Mil)
Source current
32 mA (Com’l),
12 mA (Mil)
High-speed parallel latches
Buffered common latch enable inpu
t
Functional Description
The FCT841T bus interface latch is designed to eliminate the
extra packages required to buffer existing latches and provide
extra data width for wider address/data paths or buses
carrying parity. The FCT841T is a buffered 10-bit wide version
of the FCT373 function.
The FCT841T high-performance interface is designed for
high-capacitance
load
drive
low-capacitance bus loading at both inputs and outputs.
Outputs are designed for low-capacitance bus loading in the
high impedance state and are designed with a power-off
disable feature to allow for live insertion of boards.
capability
while
providing
Logic Block Diagram
Pin Configurations
D
Y
0
OE
D
0
LE
Q
Y
1
D
1
Y
2
D
2
Y
3
D
3
Y
4
D
4
Y
5
D
5
Y
N- 1
D
N- 1
Y
N
D
N
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
LE
LE
LE
LE
LE
LE
LE
D
Y
Q
LE
D
LE
OE
10
10
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
V
CC
Y
0
15
DIP/QSOP/SOIC
Top View
OE
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
LE
GND
D
0
Functional Block Diagram
LE
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