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參數(shù)資料
| 型號(hào)： | CY74FCT163646SSOP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 16-Bit Registered Transceiver |
| 中文描述： | 16位注冊(cè)收發(fā)器 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 71K |
| 代理商： | CY74FCT163646SSOP |
16-Bit Registered Transceiver
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
SCCS058 - March 1997 - Revised March 2000
CY74FCT163646
Copyright
2000, Texas Instruments Incorporated
1CY74FCT163646
Features
Low power, pin-compatible replacement for LCX and
LPT families
5V tolerant inputs and outputs
24 mA balanced drive outputs
Power-off disable outputs permits live insertion
Edge-rate control circuitry for reduced noise
FCT-C speed at 5.4 ns
Latch-up performance exceeds JEDEC standard no. 17
ESD > 2000V per MIL-STD-883D, Method 3015
Typical output skew < 250 ps
Industrial temperature range of –40C to +85C
TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
Typical V
olp
(ground bounce) performance exceeds Mil
Std 883D
V
CC
= 2.7V to 3.6V
Functional Description
The CY74FCT163646 16-bit transceiver is a three-state,
D-type register, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from the
internal registers. Data on the A or B bus will be clocked into
the registers as the appropriate clock pin goes to a HIGH logic
level. Output Enable (OE) and direction pins (DIR) are
provided to control the transceiver function. In the transceiver
mode, data present at the high impedance port may be stored
in either the A or B register, or in both. The select controls can
multiplex stored and real-time (transparent mode) data. The
direction control determines which bus will receive data when
the Output Enable (OE) is Active LOW. In the isolation mode
(Output Enable (OE) HIGH), A data may be stored in the B
register and/or B data may be stored in the A register.
The CY74FCT163646 has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The inputs
and outputs were designed to be capable of being driven by
5.0V buses, allowing them to be used in mixed voltage
systems as translators. The outputs are also designed with a
power-off disable feature enabling them to be used in
applications requiring live insertion.
Logic Block Diagrams
C
D
1B1
C
D
1A1
TO 7 OTHER CHANNELS
1SAB
1CLKAB
1C1SBA
1DIR
1OE
B REG
A REG
C
D
2B1
C
D
2A1
2SAB
2CLKAB
2C2SBA
2DIR
2OE
B REG
TO 7 OTHER CHANNELS
A REG
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CY74FCT163646TSSOP | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:16-Bit Registered Transceiver |
| CY74FCT163652 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:16-Bit Registered Transceiver |
| CY74FCT163652APAC | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:16-Bit Registered Transceiver |
| CY74FCT163652APACT | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:16-Bit Registered Transceiver |
| CY74FCT163652CPAC | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:16-Bit Registered Transceiver |
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