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參數(shù)資料
| 型號： | CY64146V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4M (256K x 16) Static RAM |
| 中文描述： | 4分（256K × 16）靜態(tài)RAM |
| 文件頁數(shù)： | 5/10頁 |
| 文件大小： | 234K |
| 代理商： | CY64146V |
CY62146V MoBL
Document #: 38-05159 Rev. *A
Page 5 of 10
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BHE / BLE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
[7, 8]
WE HIGH to Low-Z
[7]
60
60
0
0
40
60
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
10
Switching Characteristics
Over the Operating Range (continued)
[6]
Parameter
Description
70 ns
Unit
Min.
Max.
Switching Waveforms
Notes:
11.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
Device is continuously selected. OE, CE = V
IL
.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
Read Cycle No. 1
[11, 12]
50%
50%
DATA VALID
t
RC
t
ACE
t
DBE
t
LZBE
t
LZCE
t
PU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
I
CC
I
SB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
V
SUPPLY
CURRENT
Read Cycle No. 2
[12, 13]
t
HZBE
BHE/BLE
t
DOE
t
LZOE
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