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參數(shù)資料
| 型號(hào)： | CY64146V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4M (256K x 16) Static RAM |
| 中文描述： | 4分（256K × 16）靜態(tài)RAM |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 234K |
| 代理商： | CY64146V |
CY62146V MoBL
Document #: 38-05159 Rev. *A
Page 4 of 10
Parameter
R1
R2
R
TH
V
TH
3.0V
1105
1550
645
1.75
Unit
Ohms
Ohms
Ohms
V
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
Description
Conditions
Min. Typ.
[3]
Max.
1.0
1
Unit
V
μ
A
V
CC
for Data Retention)
Data Retention Current
3.6
10
V
CC
= 1.0V, CE > V
CC
–
0.3V, V
IN
> V
CC
–
0.3V or V
IN
<
0.3V; No input may exceed V
CC
+ 0.3V
t
CDR[4]
Chip Deselect to Data
Retention Time
Operation Recovery Time
0
ns
t
R[5]
Data Retention Waveform
70
ns
V
CC(min.)
V
CC(min.)
t
CDR
V
DR
> 1.0 V
DATA RETENTION MODE
t
R
CE
V
CC
Switching Characteristics
Over the Operating Range
[6]
Parameter
Description
70 ns
Unit
Min.
Max.
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[9, 10]
t
WC
Notes:
5.
Full Device AC operation requires linear V
ramp from V
to V
> 10
μ
s or stable V
>10
μ
s.
6.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to V
CC(typ.)
, and output loading of the specified
I
/I
and 30 pF load capacitance.
7.
At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
8.
t
, t
, and t
are specified with C
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
9.
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[7, 8]
OE HIGH to High-Z
[8]
CE LOW to Low-Z
[7]
CE HIGH to High-Z
[7, 8]
CE LOW to Power-up
CE HIGH to Power-down
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low-Z
BHE / BLE HIGH to High-Z
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
10
70
25
5
20
10
20
0
70
35
5
20
Write Cycle Time
70
ns
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