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參數(shù)資料
| 型號： | CY6264-70SNC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | Single Supply RS232C Line Driver/Receiver(?????μ?o?RS232C ?o?????????¨???2???2??????) |
| 中文描述： | 8K X 8 STANDARD SRAM, 70 ns, PDSO28 |
| 封裝： | 0.300 INCH, SNC-28 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 253K |
| 代理商： | CY6264-70SNC |
PRELIMINARY
8K x 8 Static RAM
CY6264
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
October 1994 – Revised June 1996
408-943-2600
1CY6264
Features
55, 70 ns access times
CMOS for optimum speed/power
Easy memory expansion with CE
1
, CE
2
, and OE fea-
tures
TTL-compatible inputs and outputs
Automatic power-down when deselected
Functional Description
The CY6264 is a high-performance CMOS static RAM orga-
nized as 8192 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE
1
), an active HIGH
chip enable (CE
2
), and active LOW output enable (OE) and
three-state drivers. Both devices have an automatic pow-
er-down feature (CE
1
), reducing the power consumption by
over 70% when deselected. The CY6264 is packaged in a
450-mil (300-mil body) SOIC.
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE
1
and WE in-
puts are both LOW and CE
2
is HIGH, data on the eight data
input/output pins (I/O
0
through I/O
7
) is written into the memory
location addressed by the address present on the address
pins (A
0
through A
12
). Reading the device is accomplished by
selecting the device and enabling the outputs, CE
1
and OE
active LOW, CE
2
active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location ad-
dressed by the information on address pins is present on the
eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configuration
CY6264-1
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
I/O
0
CY6264-2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
CE
2
A
3
A
2
A
1
OE
A
0
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
NC
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
I/O
0
I/O
1
I/O
2
GND
256 x 32 x 8
ARRAY
INPUT BUFFER
COLUMN DECODER
POWER
DOWN
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CE
1
CE
2
WE
OE
Top View
SOIC
Selection Guide
CY6264-55
CY6264-70
Maximum Access Time (ns)
55
70
Maximum Operating Current (mA)
100
100
Maximum Standby Current (mA)
20/15
20/15
Shaded area contains advanced information.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY6264-55SNC | 8K x 8 Static RAM |
| CY6264 | 8K x 8 Static RAM(8K x 8 靜態(tài)RAM) |
| CY7B923-155JI | HOTLink⑩ Transmitter/Receiver |
| CY7B923 | HOTLink⑩ Transmitter/Receiver |
| CY7B923-SC | HOTLink⑩ Transmitter/Receiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY6264-70SNCT | 制造商:Cypress Semiconductor 功能描述: |
| CY6264-70SNI | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| CY6264-70SNIT | 制造商:Cypress Semiconductor 功能描述: |
| CY6264-70SNXA | 功能描述:靜態(tài)隨機(jī)存取存儲器 SLO 5.0V STD PWR 8KX8 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY6264-70SNXAT | 功能描述:靜態(tài)隨機(jī)存取存儲器 SLO 5.0V STD PWR 8KX8 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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