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參數(shù)資料
| 型號(hào)： | CY62256VN |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256K (32K x 8) Static RAM |
| 中文描述： | 256K（32K的× 8）靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大小： | 641K |
| 代理商： | CY62256VN |
CY62256VN
Document #: 001-06512 Rev. *A
Page 5 of 12
Switching Characteristics
Over the Operating Range
[7]
Parameter
Description
CY62256VN-70
Min.
Unit
Max.
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[10, 11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Notes:
7. Test conditions assume signal transition time of 5 ns or less timing reference levels of V
CC
/2, input pulse levels of 0 to V
CC
, and output loading of the specified
I
/I
and 100-pF load capacitance.
8. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
9. t
, t
, and t
are specified with C
= 5 pF as in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
10.The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[8]
OE HIGH to High-Z
[8, 9]
CE LOW to Low-Z
[8]
CE HIGH to High-Z
[8, 9]
CE LOW to Power-up
CE HIGH to Power-down
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
10
70
35
5
25
10
25
0
70
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
[8, 9]
WE HIGH to Low-Z
[8]
70
60
60
0
0
50
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
10
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62256VNLL-70SNC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY62256VNLL-70SNXC | 功能描述:IC SRAM 256KBIT 70NS 28SOIC RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:MoBL® 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱(chēng):557-1327-2 |
| CY62256VNLL-70SNXCT | 功能描述:IC SRAM 256KBIT 70NS 28SOIC RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:MoBL® 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱(chēng):557-1327-2 |
| CY62256VNLL-70SNXE | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 SLO 3.0V ULTRA LO PWR 32KX8 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62256VNLL-70SNXET | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 SLO 3.0V ULTRA LO PWR 32KX8 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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