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參數(shù)資料
| 型號： | CY62256V25LL |
| 廠商： | Cypress Semiconductor Corp. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Single Supply RS232C Line Driver/Receiver(?????μ?o?RS232C ?o?????????¨???2???2??????) |
| 中文描述： | 單電源RS232C接口線路驅(qū)動器/接收器（單電源RS232C接口線收發(fā)器（2發(fā)2收）） |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 388K |
| 代理商： | CY62256V25LL |
256K (32K x 8) Static RAM
CY62256V
Cypress Semiconductor Corporation
Document #: 38-05057 Rev. *D
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised June 28, 2004
Features
Temperature Ranges
—Commercial: 0°C to 70°C
—Industrial: –40°C to 85°C
—Automotive: –40°C to 125°C
Speed: 70 ns and 100 ns
Low voltage range:
—CY62256V (2.7V–3.6V)
—CY62256V25 (2.3V–2.7V)
Low active power and standby power
Easy memory expansion with CE and OE features
TTL-compatible inputs and outputs
Automatic power-down when deselected
CMOS for optimum speed/power
Package available in a standard 450-mil-wide (300-mil
body width) 28-lead narrow SOIC, 28-lead TSOP-1, and
reverse 28-lead TSOP-1 package
Functional Description
[1]
The CY62256V family is composed of two high-performance
CMOS static RAM’s organized as 32K words by 8 bits. Easy
memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and three-state
drivers. These devices have an automatic power-down
feature, reducing the power consumption by over 99% when
deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
0
through I/O
7
) is written into the memory location
addressed by the address present on the address pins (A
0
through A
14
). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
Note:
1.
For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
COLUMN
DECODER
R
S
INPUTBUFFER
POWER
DOWN
WE
OE
I/O
0
CE
I/O
1
I/O
2
I/O
3
512 × 512
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
10
A
1
A
1
A
1
A
0
A
1
A
1
Logic Block Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62256V-70SNC | 32K x 8 Static RAM |
| CY62256V-70ZC | 32K x 8 Static RAM |
| CY62256VL-55RZC | 32K x 8 Static RAM |
| CY62256VL-55SNC | 32K x 8 Static RAM |
| CY62256VL-55ZC | 32K x 8 Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62256V-70SNCT | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY62256V-70ZC | 制造商:Cypress Semiconductor 功能描述: |
| CY62256VL-70SNC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 256K-Bit 32K x 8 70ns 28-Pin SNC 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY62256VL-70SNCT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| CY62256VL-70ZI | 制造商:Cypress Semiconductor 功能描述: |
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