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參數(shù)資料
| 型號： | CY62177DV30L-70BAI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 16-Mbit (2M x 8) Static RAM |
| 中文描述： | 2M X 16 STANDARD SRAM, 70 ns, PBGA48 |
| 封裝： | 8 X 9.50 MM, 1.20 MM HEIGHT, FBGA-48 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 856K |
| 代理商： | CY62177DV30L-70BAI |
Document #: 001-07721 Rev. *B
Page 5 of 10
CY62168EV30 MoBL
Switching Characteristics
Over the Operating Range
[11]
Parameter
Description
45 ns
Unit
Min
Max
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[14]
Read Cycle Time
45
ns
Address to Data Valid
45
ns
Data Hold from Address Change
10
ns
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[12]
OE HIGH to High Z
[12, 13]
CE
1
LOW and CE
2
HIGH to Low Z
[12]
CE
1
HIGH or CE
2
LOW to High Z
[12, 13]
CE
1
LOW and CE
2
HIGH to Power Up
CE
1
HIGH or CE
2
LOW to Power Down
45
ns
22
ns
5
ns
18
ns
10
ns
18
ns
0
ns
45
ns
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
45
ns
CE
1
LOW and CE
2
HIGH to Write End
Address Setup to Write End
35
ns
35
ns
Address Hold from Write End
0
ns
Address Setup to Write Start
0
ns
WE Pulse Width
35
ns
Data Setup to Write End
25
ns
Data Hold from Write End
WE LOW to High Z
[12, 13]
WE HIGH to Low Z
[12]
0
ns
18
ns
10
ns
Notes
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1V/ns), timing reference levels of V
CC
(typ)/2, input
pulse levels of 0 to V
(typ), and output loading of the specified I
OL
/I
OH
as shown in
“AC Test Loads and Waveforms” on page 4
.
12.At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
HZWE
is less than t
LZWE
for any given device.
13.t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
14.The internal write time of the memory is defined by the overlap of WE, CE
= V
, and CE
= V
. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62177DV30L-70BAIES | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY62177DV30LL5-55BAXI | 制造商:Cypress Semiconductor 功能描述: |
| CY62177DV30LL-55BAI | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| CY62177DV30LL-55BAXI | 功能描述:靜態(tài)隨機(jī)存取存儲器 SLO 3V SUPER LO PWR 1MEGX 6 IND RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62177DV30LL-55BAXIT | 功能描述:靜態(tài)隨機(jī)存取存儲器 SLO 3V SUPER LO PWR 1MEGX 6 IND RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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