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參數(shù)資料
| 型號： | CY62167EV18 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Replacement for National Semiconductor part number 9334DM. Buy from authorized manufacturer Rochester Electronics. |
| 中文描述： | 16兆位（1米× 16）靜態(tài)RAM |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 459K |
| 代理商： | CY62167EV18 |
CY62167EV18 MoBL
Document #: 38-05447 Rev. *E
Page 5 of 12
Switching Characteristics
Over the Operating Range
[12, 13]
Parameter
Description
55 ns
Unit
Min
Max
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[16]
Read Cycle Time
55
ns
Address to Data Valid
55
ns
Data Hold from Address Change
10
ns
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[14]
OE HIGH to High-Z
[14, 15]
CE
1
LOW and CE
2
HIGH to Low-Z
[14]
CE
1
HIGH and CE
2
LOW to High-Z
[14, 15]
CE
1
LOW and CE
2
HIGH to Power Up
CE
1
HIGH and CE
2
LOW to Power Down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low-Z
[14]
BLE/BHE HIGH to High-Z
[14, 15]
55
ns
25
ns
5
ns
18
ns
10
ns
18
ns
0
ns
55
ns
55
ns
10
ns
18
ns
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
55
ns
CE
1
LOW and CE
2
HIGH
to Write End
Address Setup to Write End
40
ns
40
ns
Address Hold from Write End
0
ns
Address Setup to Write Start
0
ns
WE Pulse Width
40
ns
BLE/BHE LOW to Write End
40
ns
Data Setup to Write End
25
ns
Data Hold from Write End
WE LOW to High-Z
[14, 15]
WE HIGH to Low-Z
[14]
0
ns
20
ns
10
ns
Notes
12.Test conditions for all parameters other than tri-state parameters are based on signal transition time of 1V/ns, timing reference levels of V
CC(typ)
/2, input pulse levels
of 0 to V
, and output loading of the specified I
/I
as shown in
AC Test Loads and Waveforms on page 4
.
13.AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See
application note AN13842
for further clarification.
14.At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given
device.
15.t
, t
, t
, and t
transitions are measured when the output enters a high impedance state.
16.The internal memory write time is defined by the overlap of WE, CE
= V
, BHE and/or BLE = V
, and CE
= V
. All signals must be ACTIVE to initiate a write and
any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
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| CY62167EV18LL-55BVI | 功能描述:靜態(tài)隨機(jī)存取存儲器 16MB (1Mx16) 1.8v 55ns Async 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62167EV18LL-55BVIT | 功能描述:靜態(tài)隨機(jī)存取存儲器 16 Mbit Static RAM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62167EV18LL55BVXI | 制造商:Cypress Semiconductor 功能描述: |
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