參數(shù)資料
型號: CY62157E
廠商: Cypress Semiconductor Corp.
英文描述: 8-Mbit (512K x 16) Static RAM
中文描述: 8兆位(為512k × 16)靜態(tài)RAM
文件頁數(shù): 5/12頁
文件大小: 530K
代理商: CY62157E
CY62157E MoBL
Document #: 38-05695 Rev. *E
Page 5 of 12
Switching Characteristics
Over the Operating Range
[12, 13]
Parameter
Description
45 ns (Industrial)
55 ns (Automotive)
Unit
Min
Max
Min
Max
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[16]
Read Cycle Time
45
55
ns
Address to Data Valid
45
55
ns
Data Hold from Address Change
10
10
ns
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to LOW-Z
[14]
OE HIGH to High-Z
[14, 15]
CE
1
LOW and CE
2
HIGH to Low-Z
[14]
CE
1
HIGH and CE
2
LOW to High-Z
[14, 15]
CE
1
LOW and CE
2
HIGH to Power Up
CE
1
HIGH and CE
2
LOW to Power Down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low-Z
[14]
BLE/BHE HIGH to HIGH-Z
[14, 15]
45
55
ns
22
25
ns
5
5
ns
18
20
ns
10
10
ns
18
20
ns
0
0
ns
45
55
ns
45
55
ns
10
10
ns
18
20
ns
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
45
55
ns
CE
1
LOW and CE
2
HIGH
to Write End
Address Setup to Write End
35
35
40
40
ns
ns
Address Hold from Write End
0
0
0
0
ns
Address Setup to Write Start
ns
WE Pulse Width
35
40
ns
BLE/BHE LOW to Write End
35
25
40
25
ns
Data Setup to Write End
ns
Data Hold from Write End
WE LOW to High-Z
[14, 15]
WE HIGH to Low-Z
[14]
0
0
ns
18
20
ns
10
10
ns
Notes
12.Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of V
CC(typ)
/2, input pulse
levels of 0 to V
, and output loading of the specified I
/I
as shown in the
“AC Test Loads and Waveforms” on page 4
.
13.AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See
application note AN13842
for further clarification.
14.At any temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
15.t
, t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
16.The internal write time of the memory is defined by the overlap of WE, CE
= V
, BHE, BLE, or both = V
, and CE
= V
. All signals must be active to initiate a
write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
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