參數(shù)資料
型號(hào)： CY62157E
廠商： Cypress Semiconductor Corp.
英文描述： 8-Mbit (512K x 16) Static RAM
中文描述： 8兆位（為512k × 16）靜態(tài)RAM
文件頁數(shù)： 3/12頁
文件大?。?/td> 530K
代理商： CY62157E
CY62157E MoBL
Document #: 38-05695 Rev. *E
Page 3 of 12
Maximum Ratings
Exceeding maximum ratings may shorten the battery life of the
device. User guidelines are not tested.
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
Supply Voltage to Ground
Potential .......................................................... –0.5V to 6.0V
DC Voltage Applied to Outputs
in High-Z State
[5, 6]
........................................... –0.5V to 6.0V
DC Input Voltage
[5, 6]
........................................–0.5V to 6.0V
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage ..........................................> 2001V
(MIL-STD-883, Method 3015)
Latch up Current ....................................................> 200 mA
Operating Range
Device
Range
Ambient
Temperature
–40°C to +85°C
V
CC
[7]
CY62157ELL
Industrial
Automotive –40°C to +125°C
4.5V to 5.5V
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
45 ns (Industrial)
Typ
[2]
55 ns (Automotive)
Typ
[2]
Unit
Min
Max
Min
Max
V
OH
Output HIGH
Voltage
I
OH
= –1 mA
2.4
2.4
V
V
OL
Output LOW
Voltage
I
OL
= 2.1 mA
0.4
0.4
V
V
IH
Input HIGH
Voltage
V
CC
= 4.5V to 5.5V
2.2
V
CC
+ 0.5
2.2
V
CC
+ 0.5
V
V
IL
Input LOW
Voltage
V
CC
= 4.5V to 5.5V
–0.5
0.8
–0.5
0.8
V
I
IX
Input Leakage
Current
GND < V
I
< V
CC
–1
+1
–4
+4
μ
A
I
OZ
Output Leakage
Current
GND < V
O
< V
CC
, Output Disabled
–1
+1
–4
+4
μ
A
I
CC
V
CC
Operating
Supply
Current
f = f
max
= 1/t
RC
V
CC
= V
CC(max)
f = 1 MHz
I
OUT
= 0 mA
CMOS levels
18
25
18
35
mA
1.8
3
1.8
4
I
SB1
Automatic CE
Power Down
Current —
CMOS Inputs
CE
1
> V
CC
0.2V or CE
2
< 0.2V,
V
IN
> V
CC
– 0.2V, V
IN
< 0.2V,
f = f
max
(Address and Data Only),
f = 0 (OE, BHE, BLE and WE),
V
CC
= V
CC(max)
CE
1
> V
CC
– 0.2V or CE
2
< 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
f = 0, V
CC
= V
CC(max)
2
8
2
30
μ
A
I
SB2 [8]
Automatic CE
Power Down
Current —
CMOS Inputs
2
8
2
30
μ
A
Capacitance
[9]
Parameter
Description
Test Conditions
Max
Unit
C
IN
C
OUT
Input Capacitance
T
A
= 25°C, f = 1 MHz, V
CC
= V
CC(typ)
10
pF
Output Capacitance
10
pF
Notes
5. V
IL(min)
= –2.0V for pulse durations less than 20 ns for I < 30 mA.
6. V
= V
+ 0.75V for pulse durations less than 20 ns.
7. Full device AC operation assumes a 100
μ
s ramp time from 0 to V
(min) and 200
μ
s wait time after V
stabilization.
8. Only chip enables (CE
and CE
) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
9. Tested initially and after any design or process changes that may affect these parameters.
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